From b4e76215634413ad39db47b7cbec87fc81e14e31 Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Thu, 24 May 2018 11:54:37 -0700
Subject: Comment out assertion test, fix ref generation

---
 chiselFrontend/src/main/scala/chisel3/core/Bits.scala | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 0550a72c..adf97dbe 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -95,7 +95,11 @@ sealed abstract class Bits(width: Width)
 
   // provide bits-specific literal handling functionality here
   override private[chisel3] def ref: Arg = topBindingOpt match {
-    case Some(binding: LitBinding) => binding.asInstanceOf[ElementLitBinding].litArg
+    case Some(ElementLitBinding(litArg)) => litArg
+    case Some(BundleLitBinding(litMap)) => litMap.get(this) match {
+      case Some(litArg) => litArg
+      case _ => throwException(s"internal error: DontCare should be caught before connect")
+    }
     case _ => super.ref
   }
 
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