diff options
| author | Schuyler Eldridge | 2020-02-06 12:17:14 -0500 |
|---|---|---|
| committer | GitHub | 2020-02-06 12:17:14 -0500 |
| commit | a505d23ecfbeae91c8b3ba306c5ce186d3f08c29 (patch) | |
| tree | 20c8c011718aaff7a2068108e4af23e60ad2838c /chiselFrontend/src/main/scala/chisel3/internal | |
| parent | b171f20d945487c79b18c18a2e8db98254f6e3e9 (diff) | |
| parent | 6a3eb3188c983268fab0f64ef4681b403cc2052d (diff) | |
Merge pull request #1315 from freechipsproject/emit-orr-andr
Emit FIRRTL andr, orr for Bits.{andR, orR}
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/internal')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index a16d84bb..d98bebcd 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -47,6 +47,8 @@ object PrimOp { val NotEqualOp = PrimOp("neq") val NegOp = PrimOp("neg") val MultiplexOp = PrimOp("mux") + val AndReduceOp = PrimOp("andr") + val OrReduceOp = PrimOp("orr") val XorReduceOp = PrimOp("xorr") val ConvertOp = PrimOp("cvt") val AsUIntOp = PrimOp("asUInt") |