From 6a3eb3188c983268fab0f64ef4681b403cc2052d Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Tue, 28 Jan 2020 09:40:52 -0500 Subject: Emit FIRRTL andr, orr for Bits.{andR, orR} Change the emission strategy for Bits methods andR and orR to emit FIRRTL bitwise reduce operations andr and orr. Add two tests that assert the correct behavior of these operations in BitwiseOpsSpec. Signed-off-by: Schuyler Eldridge --- chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala | 2 ++ 1 file changed, 2 insertions(+) (limited to 'chiselFrontend/src/main/scala/chisel3/internal') diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index a16d84bb..d98bebcd 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -47,6 +47,8 @@ object PrimOp { val NotEqualOp = PrimOp("neq") val NegOp = PrimOp("neg") val MultiplexOp = PrimOp("mux") + val AndReduceOp = PrimOp("andr") + val OrReduceOp = PrimOp("orr") val XorReduceOp = PrimOp("xorr") val ConvertOp = PrimOp("cvt") val AsUIntOp = PrimOp("asUInt") -- cgit v1.2.3