diff options
| author | Jim Lawson | 2016-06-20 11:38:26 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-06-20 11:38:26 -0700 |
| commit | 3026dd214f3db3308eaf8f876d0fc03f75c577d3 (patch) | |
| tree | b6599b6d4c350a8f5567a15211906ca7812972f1 /chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala | |
| parent | d408d73a171535bd7c2ba9d0037c194022b8a62f (diff) | |
Rename "package", "import", and explicit references to "chisel3".
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala index 2126ebce..eee8d598 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala @@ -1,10 +1,10 @@ // See LICENSE for license details. -package chisel.core +package chisel3.core -import chisel.internal.Builder.pushCommand -import chisel.internal.firrtl.{ModuleIO, DefInvalid} -import chisel.internal.sourceinfo.SourceInfo +import chisel3.internal.Builder.pushCommand +import chisel3.internal.firrtl.{ModuleIO, DefInvalid} +import chisel3.internal.sourceinfo.SourceInfo /** Defines a black box, which is a module that can be referenced from within * Chisel, but is not defined in the emitted Verilog. Useful for connecting |