From 3026dd214f3db3308eaf8f876d0fc03f75c577d3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 20 Jun 2016 11:38:26 -0700
Subject: Rename "package", "import", and explicit references to "chisel3".

---
 chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
index 2126ebce..eee8d598 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
@@ -1,10 +1,10 @@
 // See LICENSE for license details.
 
-package chisel.core
+package chisel3.core
 
-import chisel.internal.Builder.pushCommand
-import chisel.internal.firrtl.{ModuleIO, DefInvalid}
-import chisel.internal.sourceinfo.SourceInfo
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl.{ModuleIO, DefInvalid}
+import chisel3.internal.sourceinfo.SourceInfo
 
 /** Defines a black box, which is a module that can be referenced from within
   * Chisel, but is not defined in the emitted Verilog. Useful for connecting
-- 
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