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| author | Schuyler Eldridge | 2019-09-25 16:49:08 -0400 |
|---|---|---|
| committer | GitHub | 2019-09-25 16:49:08 -0400 |
| commit | 9746aa39d8b005dee8a523ad85ce2059f8f1c842 (patch) | |
| tree | b4dc13fe4d30da5e6ca487848b74482cbf4c6e24 /README.md | |
| parent | f6107b19fce0c4d0a16c795c711ffe825da62b94 (diff) | |
| parent | fc472186d88b33a48bb7440396ed6a9da8485b1d (diff) | |
Merge pull request #1191 from freechipsproject/readme-fix
Use raw link for FIR filter
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -18,7 +18,7 @@ Chisel is powered by [FIRRTL (Flexible Intermediate Representation for RTL)](htt Consider an FIR filter that implements a convolution operation, as depicted in this block diagram: -<img src="https://github.com/freechipsproject/chisel3/blob/readme-fix/doc/images/fir_filter.svg?sanitize=true" width="512" /> +<img src="https://raw.githubusercontent.com/freechipsproject/chisel3/master/doc/images/fir_filter.svg?sanitize=true" width="512" /> While Chisel provides similar base primitives as synthesizable Verilog, and *could* be used as such: |