diff options
| author | Schuyler Eldridge | 2019-09-25 16:23:08 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2019-09-25 16:23:08 -0400 |
| commit | fc472186d88b33a48bb7440396ed6a9da8485b1d (patch) | |
| tree | b4dc13fe4d30da5e6ca487848b74482cbf4c6e24 /README.md | |
| parent | f6107b19fce0c4d0a16c795c711ffe825da62b94 (diff) | |
Use raw link for FIR filter
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -18,7 +18,7 @@ Chisel is powered by [FIRRTL (Flexible Intermediate Representation for RTL)](htt Consider an FIR filter that implements a convolution operation, as depicted in this block diagram: -<img src="https://github.com/freechipsproject/chisel3/blob/readme-fix/doc/images/fir_filter.svg?sanitize=true" width="512" /> +<img src="https://raw.githubusercontent.com/freechipsproject/chisel3/master/doc/images/fir_filter.svg?sanitize=true" width="512" /> While Chisel provides similar base primitives as synthesizable Verilog, and *could* be used as such: |