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| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -18,7 +18,7 @@ Chisel is powered by [FIRRTL (Flexible Intermediate Representation for RTL)](htt Consider an FIR filter that implements a convolution operation, as depicted in this block diagram: -<img src="https://github.com/freechipsproject/chisel3/blob/readme-fix/doc/images/fir_filter.svg?sanitize=true" width="512" /> +<img src="https://raw.githubusercontent.com/freechipsproject/chisel3/master/doc/images/fir_filter.svg?sanitize=true" width="512" /> While Chisel provides similar base primitives as synthesizable Verilog, and *could* be used as such: |