Merge pull request #17 from ucb-bar/typehierdia

Type hierarchy diagram -- looks good

1 files changed, 6 insertions, 0 deletions

diff --git a/README.md b/README.md
index c6d5f2b1..12423672 100644
--- a/README.md
+++ b/README.md
@@ -29,6 +29,12 @@ like:
  - Optionally, Verilog to C++ (for simulation and testing).  
  *TODO: Verilator support*
 
+### Data Types Overview
+These are the base data types for defining circuit wires (abstract types which
+may not be instantiated are greyed out):
+
+![Image](doc/images/type_hierarchy.png?raw=true)
+
 ### Chisel Tutorial
 *TODO: quick howto for running chisel-tutorial*