From 99a0490828d92f69d57f258ffdb335dddc7d9771 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 7 Oct 2015 12:45:00 -0700
Subject: Link picture to README

---
 README.md | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'README.md')

diff --git a/README.md b/README.md
index c6d5f2b1..8fd52158 100644
--- a/README.md
+++ b/README.md
@@ -29,6 +29,11 @@ like:
  - Optionally, Verilog to C++ (for simulation and testing).  
  *TODO: Verilator support*
 
+### Data Types Overview
+These are the base data types for defining circuit wires: 
+
+![Image](../master/docs/images/type_hierarchy.svg?raw=true)
+
 ### Chisel Tutorial
 *TODO: quick howto for running chisel-tutorial*
 
-- 
cgit v1.2.3


From a1561f4751361e4de7afd9a071dbec86d309455b Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 7 Oct 2015 13:05:28 -0700
Subject: Remove flowed text

---
 README.md | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'README.md')

diff --git a/README.md b/README.md
index 8fd52158..12423672 100644
--- a/README.md
+++ b/README.md
@@ -30,9 +30,10 @@ like:
  *TODO: Verilator support*
 
 ### Data Types Overview
-These are the base data types for defining circuit wires: 
+These are the base data types for defining circuit wires (abstract types which
+may not be instantiated are greyed out):
 
-![Image](../master/docs/images/type_hierarchy.svg?raw=true)
+![Image](doc/images/type_hierarchy.png?raw=true)
 
 ### Chisel Tutorial
 *TODO: quick howto for running chisel-tutorial*
-- 
cgit v1.2.3