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  - Optionally, Verilog to C++ (for simulation and testing).  
  *TODO: Verilator support*
 
+### Data Types Overview
+These are the base data types for defining circuit wires (abstract types which
+may not be instantiated are greyed out):
+
+![Image](doc/images/type_hierarchy.png?raw=true)
+
 ### Chisel Tutorial
 *TODO: quick howto for running chisel-tutorial*