diff options
| author | Jim Lawson | 2016-10-06 08:57:10 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-10-06 08:57:10 -0700 |
| commit | 82625071405672eb4a19363d6f73f359ac28a7f5 (patch) | |
| tree | dee5beff0e7333fa86c1cdcdb79c0d111114b8c9 | |
| parent | b7c6e0d1a2098b545938a5a8dfce2b1d9294532f (diff) | |
| parent | 7de30c2b893a3f24d43f2e131557430eb64f6bc8 (diff) | |
Merge branch 'master' into tobits-deprecation
108 files changed, 4603 insertions, 1616 deletions
@@ -6,10 +6,18 @@ site.includeScaladoc() ghpages.settings +import UnidocKeys._ + +lazy val customUnidocSettings = unidocSettings ++ Seq ( + doc in Compile := (doc in ScalaUnidoc).value, + target in unidoc in ScalaUnidoc := crossTarget.value / "api" +) + lazy val commonSettings = Seq ( organization := "edu.berkeley.cs", - version := "3.0", + version := "3.1-SNAPSHOT", git.remoteRepo := "git@github.com:ucb-bar/chisel3.git", + autoAPIMappings := true, scalaVersion := "2.11.7" ) @@ -50,8 +58,8 @@ lazy val chiselSettings = Seq ( }, resolvers ++= Seq( - "Sonatype Snapshots" at "http://oss.sonatype.org/content/repositories/snapshots", - "Sonatype Releases" at "http://oss.sonatype.org/content/repositories/releases" + Resolver.sonatypeRepo("snapshots"), + Resolver.sonatypeRepo("releases") ), /* Bumping "com.novocode" % "junit-interface" % "0.11", causes DelayTest testSeqReadBundle to fail @@ -94,18 +102,16 @@ lazy val chiselFrontend = (project in file("chiselFrontend")). lazy val chisel = (project in file(".")). settings(commonSettings: _*). + settings(customUnidocSettings: _*). settings(chiselSettings: _*). dependsOn(coreMacros). dependsOn(chiselFrontend). settings( + aggregate in doc := false, // Include macro classes, resources, and sources main jar. mappings in (Compile, packageBin) <++= mappings in (coreMacros, Compile, packageBin), mappings in (Compile, packageSrc) <++= mappings in (coreMacros, Compile, packageSrc), mappings in (Compile, packageBin) <++= mappings in (chiselFrontend, Compile, packageBin), mappings in (Compile, packageSrc) <++= mappings in (chiselFrontend, Compile, packageSrc) - ) - -// This is ugly. There must be a better way. -publish <<= (publish) dependsOn (publish in coreMacros, publish in chiselFrontend) - -publishLocal <<= (publishLocal) dependsOn (publishLocal in coreMacros, publishLocal in chiselFrontend) + ). + aggregate(coreMacros, chiselFrontend) diff --git a/chiselFrontend/src/main/scala/Chisel/Data.scala b/chiselFrontend/src/main/scala/Chisel/Data.scala deleted file mode 100644 index b953df71..00000000 --- a/chiselFrontend/src/main/scala/Chisel/Data.scala +++ /dev/null @@ -1,176 +0,0 @@ -// See LICENSE for license details. - -package Chisel - -import scala.language.experimental.macros - -import internal._ -import internal.Builder.pushCommand -import internal.firrtl._ -import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform} - -sealed abstract class Direction(name: String) { - override def toString: String = name - def flip: Direction -} -object INPUT extends Direction("input") { override def flip: Direction = OUTPUT } -object OUTPUT extends Direction("output") { override def flip: Direction = INPUT } -object NO_DIR extends Direction("?") { override def flip: Direction = NO_DIR } - -@deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3") -object debug { // scalastyle:ignore object.name - def apply (arg: Data): Data = arg -} - -/** Mixing in this trait flips the direction of an Aggregate. */ -trait Flipped extends Data { - this.overrideDirection(_.flip, !_) -} - -/** This forms the root of the type system for wire data types. The data value - * must be representable as some number (need not be known at Chisel compile - * time) of bits, and must have methods to pack / unpack structured data to / - * from bits. - */ -abstract class Data(dirArg: Direction) extends HasId { - def dir: Direction = dirVar - - // Sucks this is mutable state, but cloneType doesn't take a Direction arg - private var isFlipVar = dirArg == INPUT - private var dirVar = dirArg - private[Chisel] def isFlip = isFlipVar - - private[Chisel] def overrideDirection(newDir: Direction => Direction, - newFlip: Boolean => Boolean): this.type = { - this.isFlipVar = newFlip(this.isFlipVar) - for (field <- this.flatten) - (field: Data).dirVar = newDir((field: Data).dirVar) - this - } - def asInput: this.type = cloneType.overrideDirection(_ => INPUT, _ => true) - def asOutput: this.type = cloneType.overrideDirection(_ => OUTPUT, _ => false) - def flip(): this.type = cloneType.overrideDirection(_.flip, !_) - - private[Chisel] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit = - throwException(s"cannot connect ${this} and ${that}") - private[Chisel] def connect(that: Data)(implicit sourceInfo: SourceInfo): Unit = - pushCommand(Connect(sourceInfo, this.lref, that.ref)) - private[Chisel] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit = - pushCommand(BulkConnect(sourceInfo, this.lref, that.lref)) - private[Chisel] def lref: Node = Node(this) - private[Chisel] def ref: Arg = if (isLit) litArg.get else lref - private[Chisel] def cloneTypeWidth(width: Width): this.type - private[Chisel] def toType: String - - def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = this badConnect that - - def <> (that: Data)(implicit sourceInfo: SourceInfo): Unit = this badConnect that - - def cloneType: this.type - def litArg(): Option[LitArg] = None - def litValue(): BigInt = litArg.get.num - def isLit(): Boolean = litArg.isDefined - - def width: Width - final def getWidth: Int = width.get - - // While this being in the Data API doesn't really make sense (should be in - // Aggregate, right?) this is because of an implementation limitation: - // cloneWithDirection, which is private and defined here, needs flatten to - // set element directionality. - // Related: directionality is mutable state. A possible solution for both is - // to define directionality relative to the container, but these parent links - // currently don't exist (while this information may be available during - // FIRRTL emission, it would break directionality querying from Chisel, which - // does get used). - private[Chisel] def flatten: IndexedSeq[Bits] - - /** Creates an new instance of this type, unpacking the input Bits into - * structured data. - * - * This performs the inverse operation of toBits. - * - * @note does NOT assign to the object this is called on, instead creates - * and returns a NEW object (useful in a clone-and-assign scenario) - * @note does NOT check bit widths, may drop bits during assignment - * @note what fromBits assigs to must have known widths - */ - def fromBits(that: Bits): this.type = macro SourceInfoTransform.thatArg - - def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo): this.type = { - var i = 0 - val wire = Wire(this.cloneType) - val bits = - if (that.width.known && that.width.get >= wire.width.get) { - that - } else { - Wire(that.cloneTypeWidth(wire.width), init = that) - } - for (x <- wire.flatten) { - x := bits(i + x.getWidth-1, i) - i += x.getWidth - } - wire.asInstanceOf[this.type] - } - - /** Packs the value of this object as plain Bits. - * - * This performs the inverse operation of fromBits(Bits). - */ - @deprecated("Best alternative, .toUInt() or if Bits really needed, .toUInt().toBits()", "chisel3") - def toBits(): UInt = SeqUtils.do_asUInt(this.flatten)(DeprecatedSourceInfo) - - /** Reinterpret cast to a UInt. - * - * @note value not guaranteed to be preserved: for example, a SInt of width - * 3 and value -1 (0b111) would become an UInt with value 7 - */ - final def asUInt(): UInt = macro SourceInfoTransform.noArg - - def do_asUInt(implicit sourceInfo: SourceInfo): UInt - -} - -object Wire { - def apply[T <: Data](t: T): T = macro WireTransform.apply[T] - - // No source info since Scala macros don't yet support named / default arguments. - def apply[T <: Data](dummy: Int = 0, init: T): T = - do_apply(null.asInstanceOf[T], init)(UnlocatableSourceInfo) - - // No source info since Scala macros don't yet support named / default arguments. - def apply[T <: Data](t: T, init: T): T = - do_apply(t, init)(UnlocatableSourceInfo) - - def do_apply[T <: Data](t: T, init: T)(implicit sourceInfo: SourceInfo): T = { - val x = Reg.makeType(t, null.asInstanceOf[T], init) - pushCommand(DefWire(sourceInfo, x)) - pushCommand(DefInvalid(sourceInfo, x.ref)) - if (init != null) { - x := init - } - x - } -} - -object Clock { - def apply(dir: Direction = NO_DIR): Clock = new Clock(dir) -} - -// TODO: Document this. -sealed class Clock(dirArg: Direction) extends Element(dirArg, Width(1)) { - def cloneType: this.type = Clock(dirArg).asInstanceOf[this.type] - private[Chisel] override def flatten: IndexedSeq[Bits] = IndexedSeq() - private[Chisel] def cloneTypeWidth(width: Width): this.type = cloneType - private[Chisel] def toType = "Clock" - - override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match { - case _: Clock => this connect that - case _ => this badConnect that - } - - def do_asUInt(implicit sourceInfo: SourceInfo): UInt = { - throwException("clock cannot be interpreted as UInt") - } - -} diff --git a/chiselFrontend/src/main/scala/Chisel/Module.scala b/chiselFrontend/src/main/scala/Chisel/Module.scala deleted file mode 100644 index 20c9dd4a..00000000 --- a/chiselFrontend/src/main/scala/Chisel/Module.scala +++ /dev/null @@ -1,113 +0,0 @@ -// See LICENSE for license details. - -package Chisel - -import scala.collection.mutable.{ArrayBuffer, HashSet} -import scala.language.experimental.macros - -import internal._ -import internal.Builder.pushCommand -import internal.Builder.dynamicContext -import internal.firrtl._ -import internal.sourceinfo.{SourceInfo, InstTransform, UnlocatableSourceInfo} - -object Module { - /** A wrapper method that all Module instantiations must be wrapped in - * (necessary to help Chisel track internal state). - * - * @param m the Module being created - * - * @return the input module `m` with Chisel metadata properly set - */ - def apply[T <: Module](bc: => T): T = macro InstTransform.apply[T] - - def do_apply[T <: Module](bc: => T)(implicit sourceInfo: SourceInfo): T = { - // Don't generate source info referencing parents inside a module, sincce this interferes with - // module de-duplication in FIRRTL emission. - val childSourceInfo = UnlocatableSourceInfo - - val parent = dynamicContext.currentModule - val m = bc.setRefs() - m._commands.prepend(DefInvalid(childSourceInfo, m.io.ref)) // init module outputs - dynamicContext.currentModule = parent - val ports = m.computePorts - Builder.components += Component(m, m.name, ports, m._commands) - pushCommand(DefInstance(sourceInfo, m, ports)) - m.setupInParent(childSourceInfo) - } -} - -/** Abstract base class for Modules, which behave much like Verilog modules. - * These may contain both logic and state which are written in the Module - * body (constructor). - * - * @note Module instantiations must be wrapped in a Module() call. - */ -abstract class Module( - override_clock: Option[Clock]=None, override_reset: Option[Bool]=None) -extends HasId { - // _clock and _reset can be clock and reset in these 2ary constructors - // once chisel2 compatibility issues are resolved - def this(_clock: Clock) = this(Option(_clock), None) - def this(_reset: Bool) = this(None, Option(_reset)) - def this(_clock: Clock, _reset: Bool) = this(Option(_clock), Option(_reset)) - - private[Chisel] val _namespace = Builder.globalNamespace.child - private[Chisel] val _commands = ArrayBuffer[Command]() - private[Chisel] val _ids = ArrayBuffer[HasId]() - dynamicContext.currentModule = Some(this) - - /** Name of the instance. */ - val name = Builder.globalNamespace.name(getClass.getName.split('.').last) - - /** IO for this Module. At the Scala level (pre-FIRRTL transformations), - * connections in and out of a Module may only go through `io` elements. - */ - def io: Bundle - val clock = Clock(INPUT) - val reset = Bool(INPUT) - - private[Chisel] def addId(d: HasId) { _ids += d } - - private[Chisel] def ports: Seq[(String,Data)] = Vector( - ("clk", clock), ("reset", reset), ("io", io) - ) - - private[Chisel] def computePorts = for((name, port) <- ports) yield { - val bundleDir = if (port.isFlip) INPUT else OUTPUT - Port(port, if (port.dir == NO_DIR) bundleDir else port.dir) - } - - private[Chisel] def setupInParent(implicit sourceInfo: SourceInfo): this.type = { - _parent match { - case Some(p) => { - pushCommand(DefInvalid(sourceInfo, io.ref)) // init instance inputs - clock := override_clock.getOrElse(p.clock) - reset := override_reset.getOrElse(p.reset) - this - } - case None => this - } - } - - private[Chisel] def setRefs(): this.type = { - for ((name, port) <- ports) { - port.setRef(ModuleIO(this, _namespace.name(name))) - } - - // Suggest names to nodes using runtime reflection - val valNames = HashSet[String](getClass.getDeclaredFields.map(_.getName):_*) - def isPublicVal(m: java.lang.reflect.Method) = - m.getParameterTypes.isEmpty && valNames.contains(m.getName) - val methods = getClass.getMethods.sortWith(_.getName > _.getName) - for (m <- methods; if isPublicVal(m)) m.invoke(this) match { - case (id: HasId) => id.suggestName(m.getName) - case _ => - } - - // All suggestions are in, force names to every node. - _ids.foreach(_.forceName(default="T", _namespace)) - _ids.foreach(_._onModuleClose) - this - } -} diff --git a/chiselFrontend/src/main/scala/Chisel/Printf.scala b/chiselFrontend/src/main/scala/Chisel/Printf.scala deleted file mode 100644 index f068f637..00000000 --- a/chiselFrontend/src/main/scala/Chisel/Printf.scala +++ /dev/null @@ -1,36 +0,0 @@ -// See LICENSE for license details. - -package Chisel - -import scala.language.experimental.macros - -import internal._ -import internal.Builder.pushCommand -import internal.firrtl._ -import internal.sourceinfo.SourceInfo - -object printf { // scalastyle:ignore object.name - /** Prints a message in simulation. - * - * Does not fire when in reset (defined as the encapsulating Module's - * reset). If your definition of reset is not the encapsulating Module's - * reset, you will need to gate this externally. - * - * May be called outside of a Module (like defined in a function), so - * functions using printf make the standard Module assumptions (single clock - * and single reset). - * - * @param fmt printf format string - * @param data format string varargs containing data to print - */ - def apply(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) { - when (!(Builder.dynamicContext.currentModule.get.reset)) { - printfWithoutReset(fmt, data:_*) - } - } - - private[Chisel] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) { - val clock = Builder.dynamicContext.currentModule.get.clock - pushCommand(Printf(sourceInfo, Node(clock), fmt, data.map((d: Bits) => d.ref))) - } -} diff --git a/chiselFrontend/src/main/scala/Chisel/internal/Builder.scala b/chiselFrontend/src/main/scala/Chisel/internal/Builder.scala deleted file mode 100644 index d0e28b7c..00000000 --- a/chiselFrontend/src/main/scala/Chisel/internal/Builder.scala +++ /dev/null @@ -1,123 +0,0 @@ -// See LICENSE for license details. - -package Chisel.internal - -import scala.util.DynamicVariable -import scala.collection.mutable.{ArrayBuffer, HashMap} - -import Chisel._ -import Chisel.internal.firrtl._ - -private[Chisel] class Namespace(parent: Option[Namespace], keywords: Set[String]) { - private var i = 0L - private val names = collection.mutable.HashSet[String]() - - private def rename(n: String) = { i += 1; s"${n}_${i}" } - - def contains(elem: String): Boolean = { - keywords.contains(elem) || names.contains(elem) || - parent.map(_ contains elem).getOrElse(false) - } - - def name(elem: String): String = { - if (this contains elem) { - name(rename(elem)) - } else { - names += elem - elem - } - } - - def child(kws: Set[String]): Namespace = new Namespace(Some(this), kws) - def child: Namespace = child(Set()) -} - -private[Chisel] class IdGen { - private var counter = -1L - def next: Long = { - counter += 1 - counter - } -} - -private[Chisel] trait HasId { - private[Chisel] def _onModuleClose {} // scalastyle:ignore method.name - private[Chisel] val _parent = Builder.dynamicContext.currentModule - _parent.foreach(_.addId(this)) - - private[Chisel] val _id = Builder.idGen.next - override def hashCode: Int = _id.toInt - override def equals(that: Any): Boolean = that match { - case x: HasId => _id == x._id - case _ => false - } - - // Facilities for 'suggesting' a name to this. - // Post-name hooks called to carry the suggestion to other candidates as needed - private var suggested_name: Option[String] = None - private val postname_hooks = scala.collection.mutable.ListBuffer.empty[String=>Unit] - // Only takes the first suggestion! - def suggestName(name: =>String): this.type = { - if(suggested_name.isEmpty) suggested_name = Some(name) - for(hook <- postname_hooks) { hook(name) } - this - } - private[Chisel] def addPostnameHook(hook: String=>Unit): Unit = postname_hooks += hook - - // Uses a namespace to convert suggestion into a true name - // Will not do any naming if the reference already assigned. - // (e.g. tried to suggest a name to part of a Bundle) - private[Chisel] def forceName(default: =>String, namespace: Namespace): Unit = - if(_ref.isEmpty) { - val candidate_name = suggested_name.getOrElse(default) - val available_name = namespace.name(candidate_name) - setRef(Ref(available_name)) - } - - private var _ref: Option[Arg] = None - private[Chisel] def setRef(imm: Arg): Unit = _ref = Some(imm) - private[Chisel] def setRef(parent: HasId, name: String): Unit = setRef(Slot(Node(parent), name)) - private[Chisel] def setRef(parent: HasId, index: Int): Unit = setRef(Index(Node(parent), ILit(index))) - private[Chisel] def setRef(parent: HasId, index: UInt): Unit = setRef(Index(Node(parent), index.ref)) - private[Chisel] def getRef: Arg = _ref.get -} - -private[Chisel] class DynamicContext { - val idGen = new IdGen - val globalNamespace = new Namespace(None, Set()) - val components = ArrayBuffer[Component]() - var currentModule: Option[Module] = None - val errors = new ErrorLog -} - -private[Chisel] object Builder { - // All global mutable state must be referenced via dynamicContextVar!! - private val dynamicContextVar = new DynamicVariable[Option[DynamicContext]](None) - - def dynamicContext: DynamicContext = - dynamicContextVar.value getOrElse (new DynamicContext) - def idGen: IdGen = dynamicContext.idGen - def globalNamespace: Namespace = dynamicContext.globalNamespace - def components: ArrayBuffer[Component] = dynamicContext.components - - def pushCommand[T <: Command](c: T): T = { - dynamicContext.currentModule.foreach(_._commands += c) - c - } - def pushOp[T <: Data](cmd: DefPrim[T]): T = pushCommand(cmd).id - - def errors: ErrorLog = dynamicContext.errors - def error(m: => String): Unit = errors.error(m) - - def build[T <: Module](f: => T): Circuit = { - dynamicContextVar.withValue(Some(new DynamicContext)) { - errors.info("Elaborating design...") - val mod = f - mod.forceName(mod.name, globalNamespace) - errors.checkpoint() - errors.info("Done elaborating.") - - Circuit(components.last.name, components) - } - } -} diff --git a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index c0f8a354..5e88560c 100644 --- a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -1,24 +1,26 @@ // See LICENSE for license details. -package Chisel +package chisel3.core import scala.collection.immutable.ListMap import scala.collection.mutable.{ArrayBuffer, HashSet, LinkedHashMap} import scala.language.experimental.macros -import internal._ -import internal.Builder.pushCommand -import internal.firrtl._ -import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, VecTransform, SourceInfoTransform} +import chisel3.internal._ +import chisel3.internal.Builder.pushCommand +import chisel3.internal.firrtl._ +import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, VecTransform, SourceInfoTransform, UnlocatableSourceInfo} /** An abstract class for data types that solely consist of (are an aggregate * of) other Data objects. */ -sealed abstract class Aggregate(dirArg: Direction) extends Data(dirArg) { - private[Chisel] def cloneTypeWidth(width: Width): this.type = cloneType - def width: Width = flatten.map(_.width).reduce(_ + _) +sealed abstract class Aggregate extends Data { + private[core] def cloneTypeWidth(width: Width): this.type = cloneType + private[core] def width: Width = flatten.map(_.width).reduce(_ + _) + private[core] def legacyConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit = + pushCommand(BulkConnect(sourceInfo, this.lref, that.lref)) - def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten) + override def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten) } object Vec { @@ -26,10 +28,10 @@ object Vec { * * @note elements are NOT assigned by default and have no value */ - def apply[T <: Data](n: Int, gen: T): Vec[T] = new Vec(gen.cloneType, n) + def apply[T <: Data](n: Int, gen: T): Vec[T] = new Vec(gen, n) @deprecated("Vec argument order should be size, t; this will be removed by the official release", "chisel3") - def apply[T <: Data](gen: T, n: Int): Vec[T] = new Vec(gen.cloneType, n) + def apply[T <: Data](gen: T, n: Int): Vec[T] = new Vec(gen, n) /** Creates a new [[Vec]] composed of elements of the input Seq of [[Data]] * nodes. @@ -49,11 +51,30 @@ object Vec { // changing apply(elt0, elts*) to apply(elts*) causes a function collision // with apply(Seq) after type erasure. Workarounds by either introducing a // DummyImplicit or additional type parameter will break some code. + + // Check that types are homogeneous. Width mismatch for Elements is safe. require(!elts.isEmpty) - val width = elts.map(_.width).reduce(_ max _) - val vec = Wire(new Vec(elts.head.cloneTypeWidth(width), elts.length)) - for ((v, e) <- vec zip elts) - v := e + def eltsCompatible(a: Data, b: Data) = a match { + case _: Element => a.getClass == b.getClass + case _: Aggregate => Mux.typesCompatible(a, b) + } + + val t = elts.head + for (e <- elts.tail) + require(eltsCompatible(t, e), s"can't create Vec of heterogeneous types ${t.getClass} and ${e.getClass}") + + val maxWidth = elts.map(_.width).reduce(_ max _) + val vec = Wire(new Vec(t.cloneTypeWidth(maxWidth), elts.length)) + def doConnect(sink: T, source: T) = { + if (elts.head.flatten.exists(_.dir != Direction.Unspecified)) { + sink bulkConnect source + } else { + sink connect source + } + } + for ((v, e) <- vec zip elts) { + doConnect(v, e) + } vec } @@ -91,10 +112,20 @@ object Vec { * @param gen function that generates the [[Data]] that becomes the output * element */ + @deprecated("Vec.fill(n)(gen) is deprecated. Please use Vec(Seq.fill(n)(gen))", "chisel3") def fill[T <: Data](n: Int)(gen: => T): Vec[T] = macro VecTransform.fill def do_fill[T <: Data](n: Int)(gen: => T)(implicit sourceInfo: SourceInfo): Vec[T] = apply(Seq.fill(n)(gen)) + + /** Truncate an index to implement modulo-power-of-2 addressing. */ + private[core] def truncateIndex(idx: UInt, n: Int)(implicit sourceInfo: SourceInfo): UInt = { + val w = BigInt(n-1).bitLength + if (n <= 1) UInt(0) + else if (idx.width.known && idx.width.get <= w) idx + else if (idx.width.known) idx(w-1,0) + else Wire(UInt(width = w), init = idx) + } } /** A vector (array) of [[Data]] elements. Provides hardware versions of various @@ -106,49 +137,70 @@ object Vec { * @note Vecs, unlike classes in Scala's collection library, are propagated * intact to FIRRTL as a vector type, which may make debugging easier */ -sealed class Vec[T <: Data] private (gen: => T, val length: Int) - extends Aggregate(gen.dir) with VecLike[T] { +sealed class Vec[T <: Data] private (gen: T, val length: Int) + extends Aggregate with VecLike[T] { // Note: the constructor takes a gen() function instead of a Seq to enforce // that all elements must be the same and because it makes FIRRTL generation // simpler. + private val self: Seq[T] = Vector.fill(length)(gen.chiselCloneType) - private val self = IndexedSeq.fill(length)(gen) + /** + * sample_element 'tracks' all changes to the elements of self. + * For consistency, sample_element is always used for creating dynamically + * indexed ports and outputing the FIRRTL type. + * + * Needed specifically for the case when the Vec is length 0. + */ + private[core] val sample_element: T = gen.chiselCloneType - override def <> (that: Data)(implicit sourceInfo: SourceInfo): Unit = this := that + // allElements current includes sample_element + // This is somewhat weird although I think the best course of action here is + // to deprecate allElements in favor of dispatched functions to Data or + // a pattern matched recursive descent + private[chisel3] final def allElements: Seq[Element] = + (sample_element +: self).flatMap(_.allElements) /** Strong bulk connect, assigning elements in this Vec from elements in a Seq. * * @note the length of this Vec must match the length of the input Seq */ - def <> (that: Seq[T])(implicit sourceInfo: SourceInfo): Unit = this := that + def <> (that: Seq[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: CompileOptions): Unit = { + require(this.length == that.length) + for ((a, b) <- this zip that) + a <> b + } // TODO: eliminate once assign(Seq) isn't ambiguous with assign(Data) since Vec extends Seq and Data - def <> (that: Vec[T])(implicit sourceInfo: SourceInfo): Unit = this := that.asInstanceOf[Data] - - override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match { - case _: Vec[_] => this connect that - case _ => this badConnect that - } + def <> (that: Vec[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: CompileOptions): Unit = this bulkConnect that.asInstanceOf[Data] /** Strong bulk connect, assigning elements in this Vec from elements in a Seq. * * @note the length of this Vec must match the length of the input Seq */ - def := (that: Seq[T])(implicit sourceInfo: SourceInfo): Unit = { + def := (that: Seq[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: CompileOptions): Unit = { require(this.length == that.length) for ((a, b) <- this zip that) a := b } // TODO: eliminate once assign(Seq) isn't ambiguous with assign(Data) since Vec extends Seq and Data - def := (that: Vec[T])(implicit sourceInfo: SourceInfo): Unit = this connect that + def := (that: Vec[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: CompileOptions): Unit = this connect that /** Creates a dynamically indexed read or write accessor into the array. */ def apply(idx: UInt): T = { - val x = gen - x.setRef(this, idx) - x + Binding.checkSynthesizable(idx ,s"'idx' ($idx)") + val port = sample_element.chiselCloneType + val i = Vec.truncateIndex(idx, length)(UnlocatableSourceInfo) + port.setRef(this, i) + + // Bind each element of port to being whatever the base type is + // Using the head element as the sample_element + for((port_elem, model_elem) <- port.allElements zip sample_element.allElements) { + port_elem.binding = model_elem.binding + } + + port } /** Creates a statically indexed read or write accessor into the array. @@ -159,18 +211,31 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int) def read(idx: UInt): T = apply(idx) @deprecated("Use Vec.apply instead", "chisel3") - def write(idx: UInt, data: T): Unit = apply(idx).:=(data)(DeprecatedSourceInfo) + def write(idx: UInt, data: T): Unit = { + apply(idx).:=(data)(DeprecatedSourceInfo, chisel3.core.ExplicitCompileOptions.NotStrict) + } - override def cloneType: this.type = + override def cloneType: this.type = { Vec(length, gen).asInstanceOf[this.type] + } - private val t = gen - private[Chisel] def toType: String = s"${t.toType}[$length]" - private[Chisel] lazy val flatten: IndexedSeq[Bits] = + private[chisel3] def toType: String = s"${sample_element.toType}[$length]" + private[chisel3] lazy val flatten: IndexedSeq[Bits] = (0 until length).flatMap(i => this.apply(i).flatten) for ((elt, i) <- self zipWithIndex) elt.setRef(this, i) + + /** Default "pretty-print" implementation + * Analogous to printing a Seq + * Results in "Vec(elt0, elt1, ...)" + */ + def toPrintable: Printable = { + val elts = + if (length == 0) List.empty[Printable] + else self flatMap (e => List(e.toPrintable, PString(", "))) dropRight 1 + PString("Vec(") + Printables(elts) + PString(")") + } } /** A trait for [[Vec]]s containing common hardware generators for collection @@ -258,7 +323,7 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId { * Usage: extend this class (either as an anonymous or named class) and define * members variables of [[Data]] subtypes to be elements in the Bundle. */ -class Bundle extends Aggregate(NO_DIR) { +class Bundle extends Aggregate { private val _namespace = Builder.globalNamespace.child // TODO: replace with better defined FIRRTL weak-connect operator @@ -274,13 +339,6 @@ class Bundle extends Aggregate(NO_DIR) { * mySubModule.io <> io * }}} */ - override def <> (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match { - case _: Bundle => this bulkConnect that - case _ => this badConnect that - } - - // TODO: replace with better defined FIRRTL strong-connect operator - override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = this <> that lazy val elements: ListMap[String, Data] = ListMap(namedElts:_*) @@ -317,7 +375,7 @@ class Bundle extends Aggregate(NO_DIR) { /** Returns a list of elements in this Bundle. */ - private[Chisel] lazy val namedElts = { + private[core] lazy val namedElts = { val nameMap = LinkedHashMap[String, Data]() val seen = HashSet[Data]() for (m <- getClass.getMethods.sortWith(_.getName < _.getName)) { @@ -333,19 +391,20 @@ class Bundle extends Aggregate(NO_DIR) { } ArrayBuffer(nameMap.toSeq:_*) sortWith {case ((an, a), (bn, b)) => (a._id > b._id) || ((a eq b) && (an > bn))} } - private[Chisel] def toType = { + private[chisel3] def toType = { def eltPort(elt: Data): String = { - val flipStr = if (elt.isFlip) "flip " else "" + val flipStr: String = if(Data.isFirrtlFlipped(elt)) "flip " else "" s"${flipStr}${elt.getRef.name} : ${elt.toType}" } s"{${namedElts.reverse.map(e => eltPort(e._2)).mkString(", ")}}" } - private[Chisel] lazy val flatten = namedElts.flatMap(_._2.flatten) - private[Chisel] def addElt(name: String, elt: Data): Unit = + private[chisel3] lazy val flatten = namedElts.flatMap(_._2.flatten) + private[core] def addElt(name: String, elt: Data): Unit = namedElts += name -> elt - - private[Chisel] override def _onModuleClose: Unit = // scalastyle:ignore method.name + private[chisel3] override def _onModuleClose: Unit = // scalastyle:ignore method.name for ((name, elt) <- namedElts) { elt.setRef(this, _namespace.name(name)) } + + private[chisel3] final def allElements: Seq[Element] = namedElts.flatMap(_._2.allElements) override def cloneType : this.type = { // If the user did not provide a cloneType method, try invoking one of @@ -373,8 +432,24 @@ class Bundle extends Aggregate(NO_DIR) { this } } + + /** Default "pretty-print" implementation + * Analogous to printing a Map + * Results in "Bundle(elt0.name -> elt0.value, ...)" + */ + def toPrintable: Printable = { + val elts = + if (elements.isEmpty) List.empty[Printable] + else { + elements.toList.reverse flatMap { case (name, data) => + List(PString(s"$name -> "), data.toPrintable, PString(", ")) + } dropRight 1 // Remove trailing ", " + } + PString("Bundle(") + Printables(elts) + PString(")") + } } -private[Chisel] object Bundle { - val keywords = List("flip", "asInput", "asOutput", "cloneType", "toBits") +private[core] object Bundle { + val keywords = List("flip", "asInput", "asOutput", "cloneType", "chiselCloneType", "toBits", + "widthOption", "signalName", "signalPathName", "signalParent", "signalComponent") } diff --git a/chiselFrontend/src/main/scala/Chisel/Assert.scala b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala index c086f014..4782a845 100644 --- a/chiselFrontend/src/main/scala/Chisel/Assert.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala @@ -1,14 +1,14 @@ // See LICENSE for license details. -package Chisel +package chisel3.core import scala.reflect.macros.blackbox.Context import scala.language.experimental.macros -import internal._ -import internal.Builder.pushCommand -import internal.firrtl._ -import internal.sourceinfo.SourceInfo +import chisel3.internal._ +import chisel3.internal.Builder.pushCommand +import chisel3.internal.firrtl._ +import chisel3.internal.sourceinfo.SourceInfo object assert { // scalastyle:ignore object.name /** Checks for a condition to be valid in the circuit at all times. If the @@ -24,21 +24,22 @@ object assert { // scalastyle:ignore object.name * * @param cond condition, assertion fires (simulation fails) when false * @param message optional message to print when the assertion fires + * @param data optional bits to print in the message formatting * * @note currently cannot be used in core Chisel / libraries because macro * defs need to be compiled first and the SBT project is not set up to do * that */ // Macros currently can't take default arguments, so we need two functions to emulate defaults. - def apply(cond: Bool, message: String)(implicit sourceInfo: SourceInfo): Unit = macro apply_impl_msg + def apply(cond: Bool, message: String, data: Bits*)(implicit sourceInfo: SourceInfo): Unit = macro apply_impl_msg_data def apply(cond: Bool)(implicit sourceInfo: SourceInfo): Unit = macro apply_impl - def apply_impl_msg(c: Context)(cond: c.Tree, message: c.Tree)(sourceInfo: c.Tree): c.Tree = { + def apply_impl_msg_data(c: Context)(cond: c.Tree, message: c.Tree, data: c.Tree*)(sourceInfo: c.Tree): c.Tree = { import c.universe._ val p = c.enclosingPosition val condStr = s"${p.source.file.name}:${p.line} ${p.lineContent.trim}" val apply_impl_do = symbolOf[this.type].asClass.module.info.member(TermName("apply_impl_do")) - q"$apply_impl_do($cond, $condStr, _root_.scala.Some($message))($sourceInfo)" + q"$apply_impl_do($cond, $condStr, _root_.scala.Some($message), ..$data)($sourceInfo)" } def apply_impl(c: Context)(cond: c.Tree)(sourceInfo: c.Tree): c.Tree = { @@ -49,13 +50,13 @@ object assert { // scalastyle:ignore object.name q"$apply_impl_do($cond, $condStr, _root_.scala.None)($sourceInfo)" } - def apply_impl_do(cond: Bool, line: String, message: Option[String])(implicit sourceInfo: SourceInfo) { - when (!(cond || Builder.dynamicContext.currentModule.get.reset)) { + def apply_impl_do(cond: Bool, line: String, message: Option[String], data: Bits*)(implicit sourceInfo: SourceInfo) { + when (!(cond || Builder.forcedModule.reset)) { message match { - case Some(str) => printf.printfWithoutReset(s"Assertion failed: $str\n at $line\n") - case None => printf.printfWithoutReset(s"Assertion failed\n at $line\n") + case Some(str) => printf.printfWithoutReset(s"Assertion failed: $str\n at $line\n", data:_*) + case None => printf.printfWithoutReset(s"Assertion failed\n at $line\n", data:_*) } - pushCommand(Stop(sourceInfo, Node(Builder.dynamicContext.currentModule.get.clock), 1)) + pushCommand(Stop(sourceInfo, Node(Builder.forcedModule.clock), 1)) } } @@ -71,3 +72,17 @@ object assert { // scalastyle:ignore object.name Predef.assert(cond, "") } } + +object stop { // scalastyle:ignore object.name + /** Terminate execution with a failure code. */ + def apply(code: Int)(implicit sourceInfo: SourceInfo): Unit = { + when (!Builder.forcedModule.reset) { + pushCommand(Stop(sourceInfo, Node(Builder.forcedModule.clock), code)) + } + } + + /** Terminate execution, indicating success. */ + def apply()(implicit sourceInfo: SourceInfo): Unit = { + stop(0) + } +} diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala new file mode 100644 index 00000000..2599a20a --- /dev/null +++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala @@ -0,0 +1,238 @@ +// See LICENSE for license details. + +package chisel3.core + +import chisel3.internal.Builder.pushCommand +import chisel3.internal.firrtl.Connect +import scala.language.experimental.macros +import chisel3.internal.sourceinfo._ + +/** +* BiConnect.connect executes a bidirectional connection element-wise. +* +* Note that the arguments are left and right (not source and sink) so the +* intent is for the operation to be commutative. +* +* The connect operation will recurse down the left Data (with the right Data). +* An exception will be thrown if a movement through the left cannot be matched +* in the right (or if the right side has extra fields). +* +* See elemConnect for details on how the root connections are issued. +* +*/ + +object BiConnect { + // These are all the possible exceptions that can be thrown. + case class BiConnectException(message: String) extends Exception(message) + // These are from element-level connection + def BothDriversException = + BiConnectException(": Both Left and Right are drivers") + def NeitherDriverException = + BiConnectException(": Neither Left nor Right is a driver") + def UnknownDriverException = + BiConnectException(": Locally unclear whether Left or Right (both internal)") + def UnknownRelationException = + BiConnectException(": Left or Right unavailable to current module.") + // These are when recursing down aggregate types + def MismatchedVecException = + BiConnectException(": Left and Right are different length Vecs.") + def MissingLeftFieldException(field: String) = + BiConnectException(s".$field: Left Bundle missing field ($field).") + def MissingRightFieldException(field: String) = + BiConnectException(s": Right Bundle missing field ($field).") + def MismatchedException(left: String, right: String) = + BiConnectException(s": Left ($left) and Right ($right) have different types.") + + /** This function is what recursively tries to connect a left and right together + * + * There is some cleverness in the use of internal try-catch to catch exceptions + * during the recursive decent and then rethrow them with extra information added. + * This gives the user a 'path' to where in the connections things went wrong. + */ + def connect(sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Data, right: Data, context_mod: Module): Unit = + (left, right) match { + // Handle element case (root case) + case (left_e: Element, right_e: Element) => { + elemConnect(sourceInfo, connectCompileOptions, left_e, right_e, context_mod) + // TODO(twigg): Verify the element-level classes are connectable + } + // Handle Vec case + case (left_v: Vec[Data @unchecked], right_v: Vec[Data @unchecked]) => { + if(left_v.length != right_v.length) { throw MismatchedVecException } + for(idx <- 0 until left_v.length) { + try { + connect(sourceInfo, connectCompileOptions, left_v(idx), right_v(idx), context_mod) + } catch { + case BiConnectException(message) => throw BiConnectException(s"($idx)$message") + } + } + } + // Handle Bundle case + case (left_b: Bundle, right_b: Bundle) => { + // Verify right has no extra fields that left doesn't have + for((field, right_sub) <- right_b.elements) { + if(!left_b.elements.isDefinedAt(field)) { + if (connectCompileOptions.connectFieldsMustMatch) { + throw MissingLeftFieldException(field) + } + } + } + // For each field in left, descend with right + for((field, left_sub) <- left_b.elements) { + try { + right_b.elements.get(field) match { + case Some(right_sub) => connect(sourceInfo, connectCompileOptions, left_sub, right_sub, context_mod) + case None => { + if (connectCompileOptions.connectFieldsMustMatch) { + throw MissingRightFieldException(field) + } + } + } + } catch { + case BiConnectException(message) => throw BiConnectException(s".$field$message") + } + } + } + // Left and right are different subtypes of Data so fail + case (left, right) => throw MismatchedException(left.toString, right.toString) + } + + // These functions (finally) issue the connection operation + // Issue with right as sink, left as source + private def issueConnectL2R(left: Element, right: Element)(implicit sourceInfo: SourceInfo): Unit = { + pushCommand(Connect(sourceInfo, right.lref, left.ref)) + } + // Issue with left as sink, right as source + private def issueConnectR2L(left: Element, right: Element)(implicit sourceInfo: SourceInfo): Unit = { + pushCommand(Connect(sourceInfo, left.lref, right.ref)) + } + + // This function checks if element-level connection operation allowed. + // Then it either issues it or throws the appropriate exception. + def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Element, right: Element, context_mod: Module): Unit = { + import Direction.{Input, Output} // Using extensively so import these + // If left or right have no location, assume in context module + // This can occur if one of them is a literal, unbound will error previously + val left_mod: Module = left.binding.location.getOrElse(context_mod) + val right_mod: Module = right.binding.location.getOrElse(context_mod) + + val left_direction: Option[Direction] = left.binding.direction + val right_direction: Option[Direction] = right.binding.direction + // None means internal + + // CASE: Context is same module as left node and right node is in a child module + if( (left_mod == context_mod) && + (right_mod._parent.map(_ == context_mod).getOrElse(false)) ) { + // Thus, right node better be a port node and thus have a direction hint + ((left_direction, right_direction): @unchecked) match { + // CURRENT MOD CHILD MOD + case (Some(Input), Some(Input)) => issueConnectL2R(left, right) + case (None, Some(Input)) => issueConnectL2R(left, right) + + case (Some(Output), Some(Output)) => issueConnectR2L(left, right) + case (None, Some(Output)) => issueConnectR2L(left, right) + + case (Some(Input), Some(Output)) => throw BothDriversException + case (Some(Output), Some(Input)) => throw NeitherDriverException + case (_, None) => throw UnknownRelationException + } + } + + // CASE: Context is same module as right node and left node is in child module + else if( (right_mod == context_mod) && + (left_mod._parent.map(_ == context_mod).getOrElse(false)) ) { + // Thus, left node better be a port node and thus have a direction hint + ((left_direction, right_direction): @unchecked) match { + // CHILD MOD CURRENT MOD + case (Some(Input), Some(Input)) => issueConnectR2L(left, right) + case (Some(Input), None) => issueConnectR2L(left, right) + + case (Some(Output), Some(Output)) => issueConnectL2R(left, right) + case (Some(Output), None) => issueConnectL2R(left, right) + + case (Some(Input), Some(Output)) => throw NeitherDriverException + case (Some(Output), Some(Input)) => throw BothDriversException + case (None, _) => throw UnknownRelationException + } + } + + // CASE: Context is same module that both left node and right node are in + else if( (context_mod == left_mod) && (context_mod == right_mod) ) { + ((left_direction, right_direction): @unchecked) match { + // CURRENT MOD CURRENT MOD + case (Some(Input), Some(Output)) => issueConnectL2R(left, right) + case (Some(Input), None) => issueConnectL2R(left, right) + case (None, Some(Output)) => issueConnectL2R(left, right) + + case (Some(Output), Some(Input)) => issueConnectR2L(left, right) + case (Some(Output), None) => issueConnectR2L(left, right) + case (None, Some(Input)) => issueConnectR2L(left, right) + + case (Some(Input), Some(Input)) => { + if (connectCompileOptions.dontAssumeDirectionality) { + throw BothDriversException + } else { + (left.binding, right.binding) match { + case (PortBinding(_, _), PortBinding(_, _)) => throw BothDriversException + case (PortBinding(_, _), _) => issueConnectL2R(left, right) + case (_, PortBinding(_, _)) => issueConnectR2L(left, right) + case _ => throw BothDriversException + } + } + } + case (Some(Output), Some(Output)) => { + if (connectCompileOptions.dontAssumeDirectionality) { + throw BothDriversException + } else { + (left.binding, right.binding) match { + case (PortBinding(_, _), PortBinding(_, _)) => throw BothDriversException + case (PortBinding(_, _), _) => issueConnectR2L(left, right) + case (_, PortBinding(_, _)) => issueConnectL2R(left, right) + case _ => throw BothDriversException + } + } + } + case (None, None) => { + if (connectCompileOptions.dontAssumeDirectionality) { + throw UnknownDriverException + } else { + issueConnectR2L(left, right) + } + } + } + } + + // CASE: Context is the parent module of both the module containing left node + // and the module containing right node + // Note: This includes case when left and right in same module but in parent + else if( (left_mod._parent.map(_ == context_mod).getOrElse(false)) && + (right_mod._parent.map(_ == context_mod).getOrElse(false)) + ) { + // Thus both nodes must be ports and have a direction hint + ((left_direction, right_direction): @unchecked) match { + // CHILD MOD CHILD MOD + case (Some(Input), Some(Output)) => issueConnectR2L(left, right) + case (Some(Output), Some(Input)) => issueConnectL2R(left, right) + + case (Some(Input), Some(Input)) => throw NeitherDriverException + case (Some(Output), Some(Output)) => throw BothDriversException + case (_, None) => + if (connectCompileOptions.dontAssumeDirectionality) { + throw UnknownRelationException + } else { + issueConnectR2L(left, right) + } + case (None, _) => + if (connectCompileOptions.dontAssumeDirectionality) { + throw UnknownRelationException + } else { + issueConnectR2L(left, right) + } + } + } + + // Not quite sure where left and right are compared to current module + // so just error out + else throw UnknownRelationException + } +} diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binder.scala b/chiselFrontend/src/main/scala/chisel3/core/Binder.scala new file mode 100644 index 00000000..c7346dce --- /dev/null +++ b/chiselFrontend/src/main/scala/chisel3/core/Binder.scala @@ -0,0 +1,64 @@ +package chisel3.core + +/** +* A Binder is a function from UnboundBinding to some Binding. +* +* These are used exclusively by Binding.bind and sealed in order to keep +* all of them in one place. There are two flavors of Binders: +* Non-terminal (returns another UnboundBinding): These are used to reformat an +* UnboundBinding (like setting direction) before it is terminally bound. +* Terminal (returns any other Binding): Due to the nature of Bindings, once a +* Data is bound to anything but an UnboundBinding, it is forever locked to +* being that type (as it now represents something in the hardware graph). +* +* Note that some Binders require extra arguments to be constructed, like the +* enclosing Module. +*/ + +sealed trait Binder[Out <: Binding] extends Function1[UnboundBinding, Out]{ + def apply(in: UnboundBinding): Out +} + +// THE NON-TERMINAL BINDERS +// These 'rebind' to another unbound node of different direction! +case object InputBinder extends Binder[UnboundBinding] { + def apply(in: UnboundBinding) = UnboundBinding(Some(Direction.Input)) +} +case object OutputBinder extends Binder[UnboundBinding] { + def apply(in: UnboundBinding) = UnboundBinding(Some(Direction.Output)) +} +case object FlippedBinder extends Binder[UnboundBinding] { + def apply(in: UnboundBinding) = UnboundBinding(in.direction.map(_.flip)) + // TODO(twigg): flipping a None should probably be a warning/error +} +// The need for this should be transient. +case object NoDirectionBinder extends Binder[UnboundBinding] { + def apply(in: UnboundBinding) = UnboundBinding(None) +} + +// THE TERMINAL BINDERS +case object LitBinder extends Binder[LitBinding] { + def apply(in: UnboundBinding) = LitBinding() +} + +case class MemoryPortBinder(enclosure: Module) extends Binder[MemoryPortBinding] { + def apply(in: UnboundBinding) = MemoryPortBinding(enclosure) +} + +case class OpBinder(enclosure: Module) extends Binder[OpBinding] { + def apply(in: UnboundBinding) = OpBinding(enclosure) +} + +// Notice how PortBinder uses the direction of the UnboundNode +case class PortBinder(enclosure: Module) extends Binder[PortBinding] { + def apply(in: UnboundBinding) = PortBinding(enclosure, in.direction) +} + +case class RegBinder(enclosure: Module) extends Binder[RegBinding] { + def apply(in: UnboundBinding) = RegBinding(enclosure) +} + +case class WireBinder(enclosure: Module) extends Binder[WireBinding] { + def apply(in: UnboundBinding) = WireBinding(enclosure) +} + diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala new file mode 100644 index 00000000..5378f3ae --- /dev/null +++ b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala @@ -0,0 +1,211 @@ +package chisel3.core + +import chisel3.internal.Builder.{forcedModule} + +/** + * The purpose of a Binding is to indicate what type of hardware 'entity' a + * specific Data's leaf Elements is actually bound to. All Data starts as being + * Unbound (and the whole point of cloneType is to return an unbound version). + * Then, specific API calls take a Data, and return a bound version (either by + * binding the original model or cloneType then binding the clone). For example, + * Reg[T<:Data](...) returns a T bound to RegBinding. + * + * It is considered invariant that all Elements of a single Data are bound to + * the same concrete type of Binding. + * + * These bindings can be checked (e.g. checkSynthesizable) to make sure certain + * operations are valid. For example, arithemetic operations or connections can + * only be executed between synthesizable nodes. These checks are to avoid + * undefined reference errors. + * + * Bindings can carry information about the particular element in the graph it + * represents like: + * - For ports (and unbound), the 'direction' + * - For (relevant) synthesizable nodes, the enclosing Module + * + * TODO(twigg): Enrich the bindings to carry more information like the hosting + * module (when applicable), direction (when applicable), literal info (when + * applicable). Can ensure applicable data only stored on relevant nodes. e.g. + * literal info on LitBinding, direction info on UnboundBinding and PortBinding, + * etc. + * + * TODO(twigg): Currently, bindings only apply at the Element level and an + * Aggregate is considered bound via its elements. May be appropriate to allow + * Aggregates to be bound along with the Elements. However, certain literal and + * port direction information doesn't quite make sense in aggregates. This would + * elegantly handle the empty Vec or Bundle problem though. + * + * TODO(twigg): Binding is currently done via allElements. It may be more + * elegant if this was instead done as a more explicit tree walk as that allows + * for better errors. + */ + +object Binding { + // Two bindings are 'compatible' if they are the same type. + // Check currently kind of weird: just ensures same class + private def compatible(a: Binding, b: Binding): Boolean = a.getClass == b.getClass + private def compatible(nodes: Seq[Binding]): Boolean = + if(nodes.size > 1) + (for((a,b) <- nodes zip nodes.tail) yield compatible(a,b)) + .fold(true)(_&&_) + else true + + case class BindingException(message: String) extends Exception(message) + def AlreadyBoundException(binding: String) = BindingException(s": Already bound to $binding") + def NotSynthesizableException = BindingException(s": Not bound to synthesizable node, currently only Type description") + + // This recursively walks down the Data tree to look at all the leaf 'Element's + // Will build up an error string in case something goes wrong + // TODO(twigg): Make member function of Data. + // Allows oddities like sample_element to be better hidden + private def walkToBinding(target: Data, checker: Element=>Unit): Unit = target match { + case (element: Element) => checker(element) + case (vec: Vec[Data @unchecked]) => { + try walkToBinding(vec.sample_element, checker) + catch { + case BindingException(message) => throw BindingException(s"(*)$message") + } + for(idx <- 0 until vec.length) { + try walkToBinding(vec(idx), checker) + catch { + case BindingException(message) => throw BindingException(s"($idx)$message") + } + } + } + case (bundle: Bundle) => { + for((field, subelem) <- bundle.elements) { + try walkToBinding(subelem, checker) + catch { + case BindingException(message) => throw BindingException(s".$field$message") + } + } + } + } + + // Use walkToBinding to actually rebind the node type + def bind[T<:Data](target: T, binder: Binder[_<:Binding], error_prelude: String): target.type = { + try walkToBinding( + target, + element => element.binding match { + case unbound @ UnboundBinding(_) => { + element.binding = binder(unbound) + } + // If autoIOWrap is enabled and we're rebinding a PortBinding, just ignore the rebinding. + case portBound @ PortBinding(_, _) if (!(forcedModule.compileOptions.requireIOWrap) && binder.isInstanceOf[PortBinder]) => + case binding => throw AlreadyBoundException(binding.toString) + } + ) + catch { + case BindingException(message) => throw BindingException(s"$error_prelude$message") + } + target + } + + // Excepts if any root element is already bound + def checkUnbound(target: Data, error_prelude: String): Unit = { + try walkToBinding( + target, + element => element.binding match { + case unbound @ UnboundBinding(_) => {} + case binding => throw AlreadyBoundException(binding.toString) + } + ) + catch { + case BindingException(message) => throw BindingException(s"$error_prelude$message") + } + } + + // Excepts if any root element is unbound and thus not on the hardware graph + def checkSynthesizable(target: Data, error_prelude: String): Unit = { + // This is called if we support autoIOWrap + def elementOfIO(element: Element): Boolean = { + element._parent match { + case None => false + case Some(x: Module) => { + // Have we defined the IO ports for this module? If not, do so now. + if (!x.ioDefined) { + x.computePorts + element.binding match { + case SynthesizableBinding() => true + case _ => false + } + } else { + // io.flatten eliminates Clock elements, so we need to use io.allElements + val ports = x.io.allElements + val isIOElement = ports.contains(element) || element == x.clock || element == x.reset + isIOElement + } + } + } + } + try walkToBinding( + target, + element => element.binding match { + case SynthesizableBinding() => {} // OK + case binding => + // The following kludge is an attempt to provide backward compatibility + // It should be done at at higher level. + if ((forcedModule.compileOptions.requireIOWrap || !elementOfIO(element))) + throw NotSynthesizableException + else + Binding.bind(element, PortBinder(element._parent.get), "Error: IO") + } + ) + catch { + case BindingException(message) => throw BindingException(s"$error_prelude$message") + } + } +} + +// Location refers to 'where' in the Module hierarchy this lives +sealed trait Binding { + def location: Option[Module] + def direction: Option[Direction] +} + +// Constrained-ness refers to whether 'bound by Module boundaries' +// An unconstrained binding, like a literal, can be read by everyone +sealed trait UnconstrainedBinding extends Binding { + def location = None +} +// A constrained binding can only be read/written by specific modules +// Location will track where this Module is +sealed trait ConstrainedBinding extends Binding { + def enclosure: Module + def location = Some(enclosure) +} + +// An undirectioned binding means the element represents an internal node +// with no meaningful concept of a direction +sealed trait UndirectionedBinding extends Binding { def direction = None } + +// This is the default binding, represents data not yet positioned in the graph +case class UnboundBinding(direction: Option[Direction]) + extends Binding with UnconstrainedBinding + + +// A synthesizable binding is 'bound into' the hardware graph +object SynthesizableBinding { + def unapply(target: Binding): Boolean = target.isInstanceOf[SynthesizableBinding] + // Type check OK because Binding and SynthesizableBinding is sealed +} +sealed trait SynthesizableBinding extends Binding +case class LitBinding() // will eventually have literal info + extends SynthesizableBinding with UnconstrainedBinding with UndirectionedBinding + +case class MemoryPortBinding(enclosure: Module) + extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding + +// TODO(twigg): Ops between unenclosed nodes can also be unenclosed +// However, Chisel currently binds all op results to a module +case class OpBinding(enclosure: Module) + extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding + +case class PortBinding(enclosure: Module, direction: Option[Direction]) + extends SynthesizableBinding with ConstrainedBinding + +case class RegBinding(enclosure: Module) + extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding + +case class WireBinding(enclosure: Module) + extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding diff --git a/chiselFrontend/src/main/scala/Chisel/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index ee6b1dee..00d0cc14 100644 --- a/chiselFrontend/src/main/scala/Chisel/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -1,38 +1,65 @@ // See LICENSE for license details. -package Chisel +package chisel3.core import scala.language.experimental.macros -import internal._ -import internal.Builder.pushOp -import internal.firrtl._ -import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, SourceInfoTransform, SourceInfoWhiteboxTransform, +import chisel3.internal._ +import chisel3.internal.Builder.{pushCommand, pushOp} +import chisel3.internal.firrtl._ +import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, SourceInfoTransform, SourceInfoWhiteboxTransform, UIntTransform, MuxTransform} -import firrtl.PrimOp._ +import chisel3.internal.firrtl.PrimOp._ +// TODO: remove this once we have CompileOptions threaded through the macro system. +import chisel3.core.ExplicitCompileOptions.NotStrict /** Element is a leaf data type: it cannot contain other Data objects. Example * uses are for representing primitive data types, like integers and bits. */ -abstract class Element(dirArg: Direction, val width: Width) extends Data(dirArg) +abstract class Element(private[core] val width: Width) extends Data { + /** + * Elements can actually be bound to the hardware graph and thus must store + * that binding information. + */ + private[this] var _binding: Binding = UnboundBinding(None) + // Define setter/getter pairing + // Can only bind something that has not yet been bound. + private[core] def binding_=(target: Binding): Unit = _binding match { + case UnboundBinding(_) => { + _binding = target + _binding + } + case _ => throw Binding.AlreadyBoundException(_binding.toString) + // Other checks should have caught this. + } + private[core] def binding = _binding + + /** Return the binding for some bits. */ + def dir: Direction = binding.direction.getOrElse(Direction.Unspecified) + + private[chisel3] final def allElements: Seq[Element] = Seq(this) + def widthKnown: Boolean = width.known + def name: String = getRef.name + + private[core] def legacyConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit = + pushCommand(Connect(sourceInfo, this.lref, that.ref)) +} /** A data type for values represented by a single bitvector. Provides basic * bitwise operations. */ -sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: Option[LitArg]) - extends Element(dirArg, width) { +sealed abstract class Bits(width: Width, override val litArg: Option[LitArg]) + extends Element(width) { // TODO: perhaps make this concrete? // Arguments for: self-checking code (can't do arithmetic on bits) // Arguments against: generates down to a FIRRTL UInt anyways - private[Chisel] def fromInt(x: BigInt, w: Int): this.type + private[chisel3] def fromInt(x: BigInt, w: Int): this.type - private[Chisel] def flatten: IndexedSeq[Bits] = IndexedSeq(this) + private[chisel3] def flatten: IndexedSeq[Bits] = IndexedSeq(this) def cloneType: this.type = cloneTypeWidth(width) - override def <> (that: Data)(implicit sourceInfo: SourceInfo): Unit = this := that - final def tail(n: Int): UInt = macro SourceInfoTransform.nArg final def head(n: Int): UInt = macro SourceInfoTransform.nArg @@ -52,7 +79,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: case KnownWidth(x) => require(x >= n, s"Can't head($n) for width $x < $n") case UnknownWidth() => } - binop(sourceInfo, UInt(width = n), HeadOp, n) + binop(sourceInfo, UInt(Width(n)), HeadOp, n) } /** Returns the specified bit on this wire as a [[Bool]], statically @@ -67,6 +94,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: if (isLit()) { Bool(((litValue() >> x.toInt) & 1) == 1) } else { + Binding.checkSynthesizable(this, s"'this' ($this)") pushOp(DefPrim(sourceInfo, Bool(), BitsExtractOp, this.ref, ILit(x), ILit(x))) } } @@ -108,7 +136,8 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: if (isLit()) { UInt((litValue >> y) & ((BigInt(1) << w) - 1), w) } else { - pushOp(DefPrim(sourceInfo, UInt(width = w), BitsExtractOp, this.ref, ILit(x), ILit(y))) + Binding.checkSynthesizable(this, s"'this' ($this)") + pushOp(DefPrim(sourceInfo, UInt(Width(w)), BitsExtractOp, this.ref, ILit(x), ILit(y))) } } @@ -118,17 +147,28 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: final def do_apply(x: BigInt, y: BigInt)(implicit sourceInfo: SourceInfo): UInt = apply(x.toInt, y.toInt) - private[Chisel] def unop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp): T = + private[core] def unop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp): T = { + Binding.checkSynthesizable(this, s"'this' ($this)") pushOp(DefPrim(sourceInfo, dest, op, this.ref)) - private[Chisel] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: BigInt): T = + } + private[core] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: BigInt): T = { + Binding.checkSynthesizable(this, s"'this' ($this)") pushOp(DefPrim(sourceInfo, dest, op, this.ref, ILit(other))) - private[Chisel] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: Bits): T = + } + private[core] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: Bits): T = { + Binding.checkSynthesizable(this, s"'this' ($this)") + Binding.checkSynthesizable(other, s"'other' ($other)") pushOp(DefPrim(sourceInfo, dest, op, this.ref, other.ref)) - - private[Chisel] def compop(sourceInfo: SourceInfo, op: PrimOp, other: Bits): Bool = + } + private[core] def compop(sourceInfo: SourceInfo, op: PrimOp, other: Bits): Bool = { + Binding.checkSynthesizable(this, s"'this' ($this)") + Binding.checkSynthesizable(other, s"'other' ($other)") pushOp(DefPrim(sourceInfo, Bool(), op, this.ref, other.ref)) - private[Chisel] def redop(sourceInfo: SourceInfo, op: PrimOp): Bool = + } + private[core] def redop(sourceInfo: SourceInfo, op: PrimOp): Bool = { + Binding.checkSynthesizable(this, s"'this' ($this)") pushOp(DefPrim(sourceInfo, Bool(), op, this.ref)) + } /** Returns this wire zero padded up to the specified width. * @@ -211,6 +251,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: def do_asSInt(implicit sourceInfo: SourceInfo): SInt /** Reinterpret cast to Bits. */ + @deprecated("Use asUInt, which does the same thing but returns a more concrete type", "chisel3") final def asBits(): Bits = macro SourceInfoTransform.noArg def do_asBits(implicit sourceInfo: SourceInfo): Bits = asUInt() @@ -224,9 +265,9 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: def do_toBool(implicit sourceInfo: SourceInfo): Bool = { width match { - case KnownWidth(1) => this(0) - case _ => throwException(s"can't covert UInt<$width> to Bool") - } + case KnownWidth(1) => this(0) + case _ => throwException(s"can't covert UInt<$width> to Bool") + } } /** Returns this wire concatenated with `other`, where this wire forms the @@ -246,6 +287,9 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: res := that res } + + /** Default print as [[Decimal]] */ + final def toPrintable: Printable = Decimal(this) } /** Provides a set of operations to create UInt types and literals. @@ -344,19 +388,15 @@ abstract trait Num[T <: Data] { /** A data type for unsigned integers, represented as a binary bitvector. * Defines arithmetic operations between other integer types. */ -sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULit] = None) - extends Bits(dir, width, lit) with Num[UInt] { - private[Chisel] override def cloneTypeWidth(w: Width): this.type = - new UInt(dir, w).asInstanceOf[this.type] - private[Chisel] def toType = s"UInt$width" +sealed class UInt private[core] (width: Width, lit: Option[ULit] = None) + extends Bits(width, lit) with Num[UInt] { - override private[Chisel] def fromInt(value: BigInt, width: Int): this.type = - UInt(value, width).asInstanceOf[this.type] + private[core] override def cloneTypeWidth(w: Width): this.type = + new UInt(w).asInstanceOf[this.type] + private[chisel3] def toType = s"UInt$width" - override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match { - case _: UInt => this connect that - case _ => this badConnect that - } + override private[chisel3] def fromInt(value: BigInt, width: Int): this.type = + UInt(value, width).asInstanceOf[this.type] // TODO: refactor to share documentation with Num or add independent scaladoc final def unary_- (): UInt = macro SourceInfoTransform.noArg @@ -430,7 +470,7 @@ sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULi final def unary_! () : Bool = macro SourceInfoTransform.noArg - def do_unary_! (implicit sourceInfo: SourceInfo) : Bool = this === Bits(0) + def do_unary_! (implicit sourceInfo: SourceInfo) : Bool = this === UInt(0, 1) override def do_<< (that: Int)(implicit sourceInfo: SourceInfo): UInt = binop(sourceInfo, UInt(this.width + that), ShiftLeftOp, that) @@ -470,31 +510,54 @@ sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULi } // This is currently a factory because both Bits and UInt inherit it. -private[Chisel] sealed trait UIntFactory { +private[core] sealed trait UIntFactory { /** Create a UInt type with inferred width. */ - def apply(): UInt = apply(NO_DIR, Width()) - /** Create a UInt type or port with fixed width. */ - def apply(dir: Direction = NO_DIR, width: Int): UInt = apply(dir, Width(width)) - /** Create a UInt port with inferred width. */ - def apply(dir: Direction): UInt = apply(dir, Width()) - - /** Create a UInt literal with inferred width. */ - def apply(value: BigInt): UInt = apply(value, Width()) + def apply(): UInt = apply(Width()) + /** Create a UInt port with specified width. */ + def apply(width: Width): UInt = new UInt(width) + /** Create a UInt with a specified width - compatibility with Chisel2. */ + def width(width: Int): UInt = apply(Width(width)) + /** Create a UInt port with specified width. */ + def width(width: Width): UInt = new UInt(width) /** Create a UInt literal with fixed width. */ - def apply(value: BigInt, width: Int): UInt = apply(value, Width(width)) + def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width)) /** Create a UInt literal with inferred width. */ - def apply(n: String): UInt = apply(parse(n), parsedWidth(n)) - /** Create a UInt literal with fixed width. */ - def apply(n: String, width: Int): UInt = apply(parse(n), width) - - /** Create a UInt type with specified width. */ - def apply(width: Width): UInt = apply(NO_DIR, width) - /** Create a UInt port with specified width. */ - def apply(dir: Direction, width: Width): UInt = new UInt(dir, width) + def apply(n: String): UInt = Lit(n) + /** Create a UInt literal with fixed width. */ + def apply(n: String, width: Int): UInt = Lit(parse(n), width) /** Create a UInt literal with specified width. */ - def apply(value: BigInt, width: Width): UInt = { + def apply(value: BigInt, width: Width): UInt = Lit(value, width) + def Lit(value: BigInt, width: Int): UInt = Lit(value, Width(width)) + /** Create a UInt literal with inferred width. */ + def Lit(value: BigInt): UInt = Lit(value, Width()) + def Lit(n: String): UInt = Lit(parse(n), parsedWidth(n)) + /** Create a UInt literal with fixed width. */ + def Lit(n: String, width: Int): UInt = Lit(parse(n), width) + /** Create a UInt literal with specified width. */ + def Lit(value: BigInt, width: Width): UInt = { val lit = ULit(value, width) - new UInt(NO_DIR, lit.width, Some(lit)) + val result = new UInt(lit.width, Some(lit)) + // Bind result to being an Literal + result.binding = LitBinding() + result + } + + /** Create a UInt with a specified width - compatibility with Chisel2. */ + // NOTE: This resolves UInt(width = 32) + def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width)) + /** Create a UInt literal with inferred width.- compatibility with Chisel2. */ + def apply(value: BigInt): UInt = apply(value, Width()) + /** Create a UInt with a specified direction and width - compatibility with Chisel2. */ + def apply(dir: Direction, width: Int): UInt = apply(dir, Width(width)) + /** Create a UInt with a specified direction, but unspecified width - compatibility with Chisel2. */ + def apply(dir: Direction): UInt = apply(dir, Width()) + def apply(dir: Direction, wWidth: Width): UInt = { + val result = apply(wWidth) + dir match { + case Direction.Input => Input(result) + case Direction.Output => Output(result) + case Direction.Unspecified => result + } } private def parse(n: String) = { @@ -521,18 +584,14 @@ private[Chisel] sealed trait UIntFactory { object UInt extends UIntFactory -sealed class SInt private (dir: Direction, width: Width, lit: Option[SLit] = None) - extends Bits(dir, width, lit) with Num[SInt] { - private[Chisel] override def cloneTypeWidth(w: Width): this.type = - new SInt(dir, w).asInstanceOf[this.type] - private[Chisel] def toType = s"SInt$width" +sealed class SInt private (width: Width, lit: Option[SLit] = None) + extends Bits(width, lit) with Num[SInt] { - override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match { - case _: SInt => this connect that - case _ => this badConnect that - } + private[core] override def cloneTypeWidth(w: Width): this.type = + new SInt(w).asInstanceOf[this.type] + private[chisel3] def toType = s"SInt$width" - override private[Chisel] def fromInt(value: BigInt, width: Int): this.type = + override private[chisel3] def fromInt(value: BigInt, width: Int): this.type = SInt(value, width).asInstanceOf[this.type] final def unary_- (): SInt = macro SourceInfoTransform.noArg @@ -627,25 +686,46 @@ sealed class SInt private (dir: Direction, width: Width, lit: Option[SLit] = Non object SInt { /** Create an SInt type with inferred width. */ - def apply(): SInt = apply(NO_DIR, Width()) - /** Create an SInt type or port with fixed width. */ - def apply(dir: Direction = NO_DIR, width: Int): SInt = apply(dir, Width(width)) - /** Create an SInt port with inferred width. */ - def apply(dir: Direction): SInt = apply(dir, Width()) + def apply(): SInt = apply(Width()) + /** Create a SInt type or port with fixed width. */ + def apply(width: Width): SInt = new SInt(width) + /** Create a SInt type or port with fixed width. */ + def width(width: Int): SInt = apply(Width(width)) + /** Create an SInt type with specified width. */ + def width(width: Width): SInt = new SInt(width) /** Create an SInt literal with inferred width. */ - def apply(value: BigInt): SInt = apply(value, Width()) + def apply(value: BigInt): SInt = Lit(value) /** Create an SInt literal with fixed width. */ - def apply(value: BigInt, width: Int): SInt = apply(value, Width(width)) + def apply(value: BigInt, width: Int): SInt = Lit(value, width) - /** Create an SInt type with specified width. */ - def apply(width: Width): SInt = new SInt(NO_DIR, width) - /** Create an SInt port with specified width. */ - def apply(dir: Direction, width: Width): SInt = new SInt(dir, width) /** Create an SInt literal with specified width. */ - def apply(value: BigInt, width: Width): SInt = { + def apply(value: BigInt, width: Width): SInt = Lit(value, width) + + def Lit(value: BigInt): SInt = Lit(value, Width()) + def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width)) + /** Create an SInt literal with specified width. */ + def Lit(value: BigInt, width: Width): SInt = { + val lit = SLit(value, width) - new SInt(NO_DIR, lit.width, Some(lit)) + val result = new SInt(lit.width, Some(lit)) + // Bind result to being an Literal + result.binding = LitBinding() + result + } + /** Create a SInt with a specified width - compatibility with Chisel2. */ + def apply(dir: Option[Direction] = None, width: Int): SInt = apply(Width(width)) + /** Create a SInt with a specified direction and width - compatibility with Chisel2. */ + def apply(dir: Direction, width: Int): SInt = apply(dir, Width(width)) + /** Create a SInt with a specified direction, but unspecified width - compatibility with Chisel2. */ + def apply(dir: Direction): SInt = apply(dir, Width()) + def apply(dir: Direction, wWidth: Width): SInt = { + val result = apply(wWidth) + dir match { + case Direction.Input => Input(result) + case Direction.Output => Output(result) + case Direction.Unspecified => result + } } } @@ -653,13 +733,13 @@ object SInt { // operations on a Bool make sense? /** A data type for booleans, defined as a single bit indicating true or false. */ -sealed class Bool(dir: Direction, lit: Option[ULit] = None) extends UInt(dir, Width(1), lit) { - private[Chisel] override def cloneTypeWidth(w: Width): this.type = { +sealed class Bool(lit: Option[ULit] = None) extends UInt(Width(1), lit) { + private[core] override def cloneTypeWidth(w: Width): this.type = { require(!w.known || w.get == 1) - new Bool(dir).asInstanceOf[this.type] + new Bool().asInstanceOf[this.type] } - override private[Chisel] def fromInt(value: BigInt, width: Int): this.type = { + override private[chisel3] def fromInt(value: BigInt, width: Int): this.type = { require((value == 0 || value == 1) && width == 1) Bool(value == 1).asInstanceOf[this.type] } @@ -692,16 +772,36 @@ sealed class Bool(dir: Direction, lit: Option[ULit] = None) extends UInt(dir, Wi def && (that: Bool): Bool = macro SourceInfoTransform.thatArg def do_&& (that: Bool)(implicit sourceInfo: SourceInfo): Bool = this & that + + /** Reinterprets this Bool as a Clock. */ + def asClock(): Clock = macro SourceInfoTransform.noArg + + def do_asClock(implicit sourceInfo: SourceInfo): Clock = pushOp(DefPrim(sourceInfo, Clock(), AsClockOp, ref)) } object Bool { /** Creates an empty Bool. */ - def apply(dir: Direction = NO_DIR): Bool = new Bool(dir) + def apply(): Bool = new Bool() /** Creates Bool literal. */ - def apply(x: Boolean): Bool = new Bool(NO_DIR, Some(ULit(if (x) 1 else 0, Width(1)))) + def apply(x: Boolean): Bool = Lit(x) + def Lit(x: Boolean): Bool = { + val result = new Bool(Some(ULit(if (x) 1 else 0, Width(1)))) + // Bind result to being an Literal + result.binding = LitBinding() + result + } + /** Create a UInt with a specified direction and width - compatibility with Chisel2. */ + def apply(dir: Direction): Bool = { + val result = apply() + dir match { + case Direction.Input => Input(result) + case Direction.Output => Output(result) + case Direction.Unspecified => result + } + } } object Mux { @@ -730,14 +830,22 @@ object Mux { private def doMux[T <: Data](cond: Bool, con: T, alt: T)(implicit sourceInfo: SourceInfo): T = { require(con.getClass == alt.getClass, s"can't Mux between ${con.getClass} and ${alt.getClass}") + Binding.checkSynthesizable(cond, s"'cond' ($cond)") + Binding.checkSynthesizable(con, s"'con' ($con)") + Binding.checkSynthesizable(alt, s"'alt' ($alt)") val d = alt.cloneTypeWidth(con.width max alt.width) pushOp(DefPrim(sourceInfo, d, MultiplexOp, cond.ref, con.ref, alt.ref)) } + private[core] def typesCompatible[T <: Data](x: T, y: T): Boolean = { + val sameTypes = x.getClass == y.getClass + val sameElements = x.flatten zip y.flatten forall { case (a, b) => a.getClass == b.getClass && a.width == b.width } + val sameNumElements = x.flatten.size == y.flatten.size + sameTypes && sameElements && sameNumElements + } + private def doAggregateMux[T <: Data](cond: Bool, con: T, alt: T)(implicit sourceInfo: SourceInfo): T = { - require(con.getClass == alt.getClass, s"can't Mux between ${con.getClass} and ${alt.getClass}") - for ((c, a) <- con.flatten zip alt.flatten) - require(c.width == a.width, "can't Mux between aggregates of different width") + require(typesCompatible(con, alt), s"can't Mux between heterogeneous types ${con.getClass} and ${alt.getClass}") doMux(cond, con, alt) } } diff --git a/chiselFrontend/src/main/scala/Chisel/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala index b634f021..c1352566 100644 --- a/chiselFrontend/src/main/scala/Chisel/BlackBox.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala @@ -1,10 +1,12 @@ // See LICENSE for license details. -package Chisel +package chisel3.core -import internal.Builder.pushCommand -import internal.firrtl.{ModuleIO, DefInvalid} -import internal.sourceinfo.SourceInfo +import chisel3.internal.Builder.pushCommand +import chisel3.internal.firrtl.{ModuleIO, DefInvalid} +import chisel3.internal.sourceinfo.SourceInfo +// TODO: remove this once we have CompileOptions threaded through the macro system. +import chisel3.core.ExplicitCompileOptions.NotStrict /** Defines a black box, which is a module that can be referenced from within * Chisel, but is not defined in the emitted Verilog. Useful for connecting @@ -24,23 +26,31 @@ abstract class BlackBox extends Module { // The body of a BlackBox is empty, the real logic happens in firrtl/Emitter.scala // Bypass standard clock, reset, io port declaration by flattening io // TODO(twigg): ? Really, overrides are bad, should extend BaseModule.... - override private[Chisel] def ports = io.elements.toSeq + override private[core] def ports = io.elements.toSeq // Do not do reflective naming of internal signals, just name io - override private[Chisel] def setRefs(): this.type = { - for ((name, port) <- ports) { - port.setRef(ModuleIO(this, _namespace.name(name))) - } + override private[core] def setRefs(): this.type = { // setRef is not called on the actual io. // There is a risk of user improperly attempting to connect directly with io // Long term solution will be to define BlackBox IO differently as part of // it not descending from the (current) Module + for ((name, port) <- ports) { + port.setRef(ModuleIO(this, _namespace.name(name))) + } + // We need to call forceName and onModuleClose on all of the sub-elements + // of the io bundle, but NOT on the io bundle itself. + // Doing so would cause the wrong names to be assigned, since their parent + // is now the module itself instead of the io bundle. + for (id <- _ids; if id ne io) { + id.forceName(default="T", _namespace) + id._onModuleClose + } this } // Don't setup clock, reset // Cann't invalide io in one bunch, must invalidate each part separately - override private[Chisel] def setupInParent(implicit sourceInfo: SourceInfo): this.type = _parent match { + override private[core] def setupInParent(implicit sourceInfo: SourceInfo): this.type = _parent match { case Some(p) => { // Just init instance inputs for((_,port) <- ports) pushCommand(DefInvalid(sourceInfo, port.ref)) diff --git a/chiselFrontend/src/main/scala/chisel3/core/CompileOptions.scala b/chiselFrontend/src/main/scala/chisel3/core/CompileOptions.scala new file mode 100644 index 00000000..4dea39b5 --- /dev/null +++ b/chiselFrontend/src/main/scala/chisel3/core/CompileOptions.scala @@ -0,0 +1,57 @@ +// See LICENSE for license details. + +package chisel3.core + +import scala.language.experimental.macros + +trait CompileOptions { + // Should Bundle connections require a strict match of fields. + // If true and the same fields aren't present in both source and sink, a MissingFieldException, + // MissingLeftFieldException, or MissingRightFieldException will be thrown. + val connectFieldsMustMatch: Boolean + // When creating an object that takes a type argument, the argument must be unbound (a pure type). + val declaredTypeMustBeUnbound: Boolean + // Module IOs should be wrapped in an IO() to define their bindings before the reset of the module is defined. + val requireIOWrap: Boolean + // If a connection operator fails, don't try the connection with the operands (source and sink) reversed. + val dontTryConnectionsSwapped: Boolean + // If connection directionality is not explicit, do not use heuristics to attempt to determine it. + val dontAssumeDirectionality: Boolean + // Issue a deprecation warning if Data.{flip, asInput,asOutput} is used + // instead of Flipped, Input, or Output. + val deprecateOldDirectionMethods: Boolean + // Check that referenced Data have actually been declared. + val checkSynthesizable: Boolean +} + +object CompileOptions { + // Provides a low priority Strict default. Can be overridden by importing the NotStrict option. + implicit def materialize: CompileOptions = chisel3.core.ExplicitCompileOptions.Strict +} + +object ExplicitCompileOptions { + // Collection of "not strict" connection compile options. + // These provide compatibility with existing code. + // import chisel3.core.ExplicitCompileOptions.NotStrict + implicit object NotStrict extends CompileOptions { + val connectFieldsMustMatch = false + val declaredTypeMustBeUnbound = false + val requireIOWrap = false + val dontTryConnectionsSwapped = false + val dontAssumeDirectionality = false + val deprecateOldDirectionMethods = false + val checkSynthesizable = false + } + + // Collection of "strict" connection compile options, preferred for new code. + // import chisel3.core.ExplicitCompileOptions.Strict + implicit object Strict extends CompileOptions { + val connectFieldsMustMatch = true + val declaredTypeMustBeUnbound = true + val requireIOWrap = true + val dontTryConnectionsSwapped = true + val dontAssumeDirectionality = true + val deprecateOldDirectionMethods = true + val checkSynthesizable = true + } +} diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala new file mode 100644 index 00000000..0e473e7e --- /dev/null +++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala @@ -0,0 +1,323 @@ +// See LICENSE for license details. + +package chisel3.core + +import scala.language.experimental.macros + +import chisel3.internal._ +import chisel3.internal.Builder.{pushCommand, pushOp} +import chisel3.internal.firrtl._ +import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform} +import chisel3.internal.firrtl.PrimOp.AsUIntOp + +sealed abstract class Direction(name: String) { + override def toString: String = name + def flip: Direction +} +object Direction { + object Input extends Direction("input") { override def flip: Direction = Output } + object Output extends Direction("output") { override def flip: Direction = Input } + object Unspecified extends Direction("unspecified") { override def flip: Direction = Input } +} + +@deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3") +object debug { // scalastyle:ignore object.name + def apply (arg: Data): Data = arg +} + +object DataMirror { + def widthOf(target: Data): Width = target.width +} + +/** +* Input, Output, and Flipped are used to define the directions of Module IOs. +* +* Note that they currently clone their source argument, including its bindings. +* +* Thus, an error will be thrown if these are used on bound Data +*/ +object Input { + def apply[T<:Data](source: T): T = { + val target = source.chiselCloneType + Data.setFirrtlDirection(target, Direction.Input) + Binding.bind(target, InputBinder, "Error: Cannot set as input ") + } +} +object Output { + def apply[T<:Data](source: T): T = { + val target = source.chiselCloneType + Data.setFirrtlDirection(target, Direction.Output) + Binding.bind(target, OutputBinder, "Error: Cannot set as output ") + } +} +object Flipped { + def apply[T<:Data](source: T): T = { + val target = source.chiselCloneType + Data.setFirrtlDirection(target, Data.getFirrtlDirection(source).flip) + Binding.bind(target, FlippedBinder, "Error: Cannot flip ") + } +} + +object Data { + /** + * This function returns true if the FIRRTL type of this Data should be flipped + * relative to other nodes. + * + * Note that the current scheme only applies Flip to Elements or Vec chains of + * Elements. + * + * A Bundle is never marked flip, instead preferring its root fields to be marked + * + * The Vec check is due to the fact that flip must be factored out of the vec, ie: + * must have flip field: Vec(UInt) instead of field: Vec(flip UInt) + */ + private[chisel3] def isFlipped(target: Data): Boolean = target match { + case (element: Element) => element.binding.direction == Some(Direction.Input) + case (vec: Vec[Data @unchecked]) => isFlipped(vec.sample_element) + case (bundle: Bundle) => false + } + + /** This function returns the "firrtl" flipped-ness for the specified object. + * + * @param target the object for which we want the "firrtl" flipped-ness. + */ + private[chisel3] def isFirrtlFlipped(target: Data): Boolean = { + Data.getFirrtlDirection(target) == Direction.Input + } + + /** This function gets the "firrtl" direction for the specified object. + * + * @param target the object for which we want to get the "firrtl" direction. + */ + private[chisel3] def getFirrtlDirection(target: Data): Direction = target match { + case (vec: Vec[Data @unchecked]) => vec.sample_element.firrtlDirection + case _ => target.firrtlDirection + } + + /** This function sets the "firrtl" direction for the specified object. + * + * @param target the object for which we want to set the "firrtl" direction. + */ + private[chisel3] def setFirrtlDirection(target: Data, direction: Direction): Unit = target match { + case (vec: Vec[Data @unchecked]) => vec.sample_element.firrtlDirection = direction + case _ => target.firrtlDirection = direction + } + + implicit class AddDirectionToData[T<:Data](val target: T) extends AnyVal { + def asInput(implicit opts: CompileOptions): T = { + if (opts.deprecateOldDirectionMethods) + Builder.deprecated("Input(Data) should be used over Data.asInput") + Input(target) + } + def asOutput(implicit opts: CompileOptions): T = { + if (opts.deprecateOldDirectionMethods) + Builder.deprecated("Output(Data) should be used over Data.asOutput") + Output(target) + } + def flip()(implicit opts: CompileOptions): T = { + if (opts.deprecateOldDirectionMethods) + Builder.deprecated("Flipped(Data) should be used over Data.flip") + Flipped(target) + } + } +} + +/** This forms the root of the type system for wire data types. The data value + * must be representable as some number (need not be known at Chisel compile + * time) of bits, and must have methods to pack / unpack structured data to / + * from bits. + */ +abstract class Data extends HasId { + // Return ALL elements at root of this type. + // Contasts with flatten, which returns just Bits + private[chisel3] def allElements: Seq[Element] + + private[core] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit = + throwException(s"cannot connect ${this} and ${that}") + private[chisel3] def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = { + if (connectCompileOptions.checkSynthesizable) { + Binding.checkSynthesizable(this, s"'this' ($this)") + Binding.checkSynthesizable(that, s"'that' ($that)") + try { + MonoConnect.connect(sourceInfo, connectCompileOptions, this, that, Builder.forcedModule) + } catch { + case MonoConnect.MonoConnectException(message) => + throwException( + s"Connection between sink ($this) and source ($that) failed @$message" + ) + } + } else { + this legacyConnect that + } + } + private[chisel3] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = { + if (connectCompileOptions.checkSynthesizable) { + Binding.checkSynthesizable(this, s"'this' ($this)") + Binding.checkSynthesizable(that, s"'that' ($that)") + try { + BiConnect.connect(sourceInfo, connectCompileOptions, this, that, Builder.forcedModule) + } catch { + case BiConnect.BiConnectException(message) => + throwException( + s"Connection between left ($this) and source ($that) failed @$message" + ) + } + } else { + this legacyConnect that + } + } + private[chisel3] def lref: Node = Node(this) + private[chisel3] def ref: Arg = if (isLit) litArg.get else lref + private[core] def cloneTypeWidth(width: Width): this.type + private[chisel3] def toType: String + private[core] def width: Width + private[core] def legacyConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit + + def cloneType: this.type + def chiselCloneType: this.type = { + // Call the user-supplied cloneType method + val clone = this.cloneType + Data.setFirrtlDirection(clone, Data.getFirrtlDirection(this)) + //TODO(twigg): Do recursively for better error messages + for((clone_elem, source_elem) <- clone.allElements zip this.allElements) { + clone_elem.binding = UnboundBinding(source_elem.binding.direction) + } + clone + } + final def := (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.connect(that)(sourceInfo, connectionCompileOptions) + final def <> (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.bulkConnect(that)(sourceInfo, connectionCompileOptions) + def litArg(): Option[LitArg] = None + def litValue(): BigInt = litArg.get.num + def isLit(): Boolean = litArg.isDefined + + /** Returns the width, in bits, if currently known. + * @throws java.util.NoSuchElementException if the width is not known. */ + final def getWidth: Int = width.get + /** Returns whether the width is currently known. */ + final def isWidthKnown: Boolean = width.known + /** Returns Some(width) if the width is known, else None. */ + final def widthOption: Option[Int] = if (isWidthKnown) Some(getWidth) else None + + // While this being in the Data API doesn't really make sense (should be in + // Aggregate, right?) this is because of an implementation limitation: + // cloneWithDirection, which is private and defined here, needs flatten to + // set element directionality. + // Related: directionality is mutable state. A possible solution for both is + // to define directionality relative to the container, but these parent links + // currently don't exist (while this information may be available during + // FIRRTL emission, it would break directionality querying from Chisel, which + // does get used). + private[chisel3] def flatten: IndexedSeq[Bits] + + /** Creates an new instance of this type, unpacking the input Bits into + * structured data. + * + * This performs the inverse operation of toBits. + * + * @note does NOT assign to the object this is called on, instead creates + * and returns a NEW object (useful in a clone-and-assign scenario) + * @note does NOT check bit widths, may drop bits during assignment + * @note what fromBits assigs to must have known widths + */ + def fromBits(that: Bits): this.type = macro SourceInfoTransform.thatArg + + def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo): this.type = { + var i = 0 + val wire = Wire(this.chiselCloneType) + val bits = + if (that.width.known && that.width.get >= wire.width.get) { + that + } else { + Wire(that.cloneTypeWidth(wire.width), init = that) + } + for (x <- wire.flatten) { + x := bits(i + x.getWidth-1, i) + i += x.getWidth + } + wire.asInstanceOf[this.type] + } + + /** Packs the value of this object as plain Bits. + * + * This performs the inverse operation of fromBits(Bits). + */ + @deprecated("Best alternative, .toUInt() or if Bits really needed, .toUInt().toBits()", "chisel3") + def toBits(): UInt = SeqUtils.do_asUInt(this.flatten)(DeprecatedSourceInfo) + + /** Reinterpret cast to UInt. + * + * @note value not guaranteed to be preserved: for example, a SInt of width + * 3 and value -1 (0b111) would become an UInt with value 7 + * @note Aggregates are recursively packed with the first element appearing + * in the least-significant bits of the result. + */ + final def asUInt(): UInt = macro SourceInfoTransform.noArg + + def do_asUInt(implicit sourceInfo: SourceInfo): UInt = + SeqUtils.do_asUInt(this.flatten)(sourceInfo) + + // firrtlDirection is the direction we report to firrtl. + // It maintains the user-specified value (as opposed to the "actual" or applied/propagated value). + // NOTE: This should only be used for emitting acceptable firrtl. + // The Element.dir should be used for any tests involving direction. + private var firrtlDirection: Direction = Direction.Unspecified + /** Default pretty printing */ + def toPrintable: Printable +} + +object Wire { + def apply[T <: Data](t: T): T = macro WireTransform.apply[T] + + // No source info since Scala macros don't yet support named / default arguments. + def apply[T <: Data](dummy: Int = 0, init: T): T = + do_apply(null.asInstanceOf[T], init)(UnlocatableSourceInfo) + + // No source info since Scala macros don't yet support named / default arguments. + def apply[T <: Data](t: T, init: T): T = + do_apply(t, init)(UnlocatableSourceInfo) + + def do_apply[T <: Data](t: T, init: T)(implicit sourceInfo: SourceInfo): T = { + val x = Reg.makeType(chisel3.core.ExplicitCompileOptions.NotStrict, t, null.asInstanceOf[T], init) + + // Bind each element of x to being a Wire + Binding.bind(x, WireBinder(Builder.forcedModule), "Error: t") + + pushCommand(DefWire(sourceInfo, x)) + pushCommand(DefInvalid(sourceInfo, x.ref)) + if (init != null) { + Binding.checkSynthesizable(init, s"'init' ($init)") + x := init + } + x + } +} + +object Clock { + def apply(): Clock = new Clock + def apply(dir: Direction): Clock = { + val result = apply() + dir match { + case Direction.Input => Input(result) + case Direction.Output => Output(result) + case Direction.Unspecified => result + } + } +} + +// TODO: Document this. +sealed class Clock extends Element(Width(1)) { + def cloneType: this.type = Clock().asInstanceOf[this.type] + private[chisel3] override def flatten: IndexedSeq[Bits] = IndexedSeq() + private[core] def cloneTypeWidth(width: Width): this.type = cloneType + private[chisel3] def toType = "Clock" + + override def connect (that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = that match { + case _: Clock => super.connect(that)(sourceInfo, connectCompileOptions) + case _ => super.badConnect(that)(sourceInfo) + } + + /** Not really supported */ + def toPrintable: Printable = PString("CLOCK") + + override def do_asUInt(implicit sourceInfo: SourceInfo): UInt = pushOp(DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref)) +} diff --git a/chiselFrontend/src/main/scala/Chisel/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala index e34d5499..9cd5a4d8 100644 --- a/chiselFrontend/src/main/scala/Chisel/Mem.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala @@ -1,13 +1,15 @@ // See LICENSE for license details. -package Chisel +package chisel3.core import scala.language.experimental.macros -import internal._ -import internal.Builder.pushCommand -import internal.firrtl._ -import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, MemTransform} +import chisel3.internal._ +import chisel3.internal.Builder.pushCommand +import chisel3.internal.firrtl._ +import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, MemTransform} +// TODO: remove this once we have CompileOptions threaded through the macro system. +import chisel3.core.ExplicitCompileOptions.NotStrict object Mem { @deprecated("Mem argument order should be size, t; this will be removed by the official release", "chisel3") @@ -19,9 +21,11 @@ object Mem { * @param t data type of memory element */ def apply[T <: Data](size: Int, t: T): Mem[T] = macro MemTransform.apply[T] - def do_apply[T <: Data](size: Int, t: T)(implicit sourceInfo: SourceInfo): Mem[T] = { - val mt = t.cloneType + val mt = t.chiselCloneType + Binding.bind(mt, NoDirectionBinder, "Error: fresh t") + // TODO(twigg): Remove need for this Binding + val mem = new Mem(mt, size) pushCommand(DefMemory(sourceInfo, mem, mt, size)) // TODO multi-clock mem @@ -34,7 +38,10 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi /** Creates a read accessor into the memory with static addressing. See the * class documentation of the memory for more detailed information. */ - def apply(idx: Int): T = apply(UInt(idx)) + def apply(idx: Int): T = { + require(idx >= 0 && idx < length) + apply(UInt(idx)) + } /** Creates a read/write accessor into the memory with dynamic addressing. * See the class documentation of the memory for more detailed information. @@ -60,7 +67,7 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi * * @param idx memory element index to write into * @param data new data to write - * @param mask write mask as a Vec of Bool: a write to the Vec element in + * @param mask write mask as a Seq of Bool: a write to the Vec element in * memory is only performed if the corresponding mask index is true. * * @note this is only allowed if the memory's element data type is a Vec @@ -79,9 +86,18 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi when (cond) { port := datum } } - private def makePort(sourceInfo: SourceInfo, idx: UInt, dir: MemPortDirection): T = - pushCommand(DefMemPort(sourceInfo, - t.cloneType, Node(this), dir, idx.ref, Node(idx._parent.get.clock))).id + private def makePort(sourceInfo: SourceInfo, idx: UInt, dir: MemPortDirection): T = { + Binding.checkSynthesizable(idx, s"'idx' ($idx)") + val i = Vec.truncateIndex(idx, length)(sourceInfo) + + val port = pushCommand( + DefMemPort(sourceInfo, + t.chiselCloneType, Node(this), dir, i.ref, Node(i._parent.get.clock)) + ).id + // Bind each element of port to being a MemoryPort + Binding.bind(port, MemoryPortBinder(Builder.forcedModule), "Error: Fresh t") + port + } } /** A combinational-read, sequential-write memory. @@ -107,7 +123,10 @@ object SeqMem { def apply[T <: Data](size: Int, t: T): SeqMem[T] = macro MemTransform.apply[T] def do_apply[T <: Data](size: Int, t: T)(implicit sourceInfo: SourceInfo): SeqMem[T] = { - val mt = t.cloneType + val mt = t.chiselCloneType + Binding.bind(mt, NoDirectionBinder, "Error: fresh t") + // TODO(twigg): Remove need for this Binding + val mem = new SeqMem(mt, size) pushCommand(DefSeqMemory(sourceInfo, mem, mt, size)) // TODO multi-clock mem diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala new file mode 100644 index 00000000..55522b4a --- /dev/null +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -0,0 +1,211 @@ +// See LICENSE for license details. + +package chisel3.core + +import scala.collection.mutable.ArrayBuffer +import scala.language.experimental.macros +import chisel3.internal._ +import chisel3.internal.Builder._ +import chisel3.internal.firrtl._ +import chisel3.internal.firrtl.{Command => _, _} +import chisel3.internal.sourceinfo.{InstTransform, SourceInfo, UnlocatableSourceInfo} + +object Module { + /** A wrapper method that all Module instantiations must be wrapped in + * (necessary to help Chisel track internal state). + * + * @param m the Module being created + * + * @return the input module `m` with Chisel metadata properly set + */ + def apply[T <: Module](bc: => T): T = macro InstTransform.apply[T] + + def do_apply[T <: Module](bc: => T)(implicit sourceInfo: SourceInfo): T = { + // Don't generate source info referencing parents inside a module, sincce this interferes with + // module de-duplication in FIRRTL emission. + val childSourceInfo = UnlocatableSourceInfo + + val parent: Option[Module] = Builder.currentModule + val m = bc.setRefs() // This will set currentModule! + m._commands.prepend(DefInvalid(childSourceInfo, m.io.ref)) // init module outputs + Builder.currentModule = parent // Back to parent! + val ports = m.computePorts + val component = Component(m, m.name, ports, m._commands) + m._component = Some(component) + Builder.components += component + // Avoid referencing 'parent' in top module + if(!Builder.currentModule.isEmpty) { + pushCommand(DefInstance(sourceInfo, m, ports)) + m.setupInParent(childSourceInfo) + } + m + } +} + +/** Abstract base class for Modules, which behave much like Verilog modules. + * These may contain both logic and state which are written in the Module + * body (constructor). + * + * @note Module instantiations must be wrapped in a Module() call. + */ +abstract class Module( + override_clock: Option[Clock]=None, override_reset: Option[Bool]=None) + (implicit moduleCompileOptions: CompileOptions) +extends HasId { + // _clock and _reset can be clock and reset in these 2ary constructors + // once chisel2 compatibility issues are resolved + def this(_clock: Clock)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), None)(moduleCompileOptions) + def this(_reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(None, Option(_reset))(moduleCompileOptions) + def this(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), Option(_reset))(moduleCompileOptions) + + // This function binds the iodef as a port in the hardware graph + private[chisel3] def Port[T<:Data](iodef: T): iodef.type = { + // Bind each element of the iodef to being a Port + Binding.bind(iodef, PortBinder(this), "Error: iodef") + iodef + } + + private[core] var ioDefined: Boolean = false + + /** + * This must wrap the datatype used to set the io field of any Module. + * i.e. All concrete modules must have defined io in this form: + * [lazy] val io[: io type] = IO(...[: io type]) + * + * Items in [] are optional. + * + * The granted iodef WILL NOT be cloned (to allow for more seamless use of + * anonymous Bundles in the IO) and thus CANNOT have been bound to any logic. + * This will error if any node is bound (e.g. due to logic in a Bundle + * constructor, which is considered improper). + * + * TODO(twigg): Specifically walk the Data definition to call out which nodes + * are problematic. + */ + def IO[T<:Data](iodef: T): iodef.type = { + require(!ioDefined, "Another IO definition for this module was already declared!") + ioDefined = true + + Port(iodef) + } + + private[core] val _namespace = Builder.globalNamespace.child + private[chisel3] val _commands = ArrayBuffer[Command]() + private[core] val _ids = ArrayBuffer[HasId]() + Builder.currentModule = Some(this) + + /** Desired name of this module. */ + def desiredName = this.getClass.getName.split('.').last + + /** Legalized name of this module. */ + final val name = Builder.globalNamespace.name(desiredName) + + /** FIRRTL Module name */ + private var _modName: Option[String] = None + private[chisel3] def setModName(name: String) = _modName = Some(name) + def modName = _modName match { + case Some(name) => name + case None => throwException("modName should be called after circuit elaboration") + } + + /** Keep component for signal names */ + private[chisel3] var _component: Option[Component] = None + + + /** Signal name (for simulation). */ + override def instanceName = + if (_parent == None) name else _component match { + case None => getRef.name + case Some(c) => getRef fullName c + } + + /** IO for this Module. At the Scala level (pre-FIRRTL transformations), + * connections in and out of a Module may only go through `io` elements. + */ + def io: Bundle + val clock = Port(Input(Clock())) + val reset = Port(Input(Bool())) + + private[chisel3] def addId(d: HasId) { _ids += d } + + private[core] def ports: Seq[(String,Data)] = Vector( + ("clock", clock), ("reset", reset), ("io", io) + ) + + private[core] def computePorts: Seq[firrtl.Port] = { + // If we're auto-wrapping IO definitions, do so now. + if (!(compileOptions.requireIOWrap || ioDefined)) { + IO(io) + } + for ((name, port) <- ports) yield { + // Port definitions need to know input or output at top-level. + // By FIRRTL semantics, 'flipped' becomes an Input + val direction = if(Data.isFirrtlFlipped(port)) Direction.Input else Direction.Output + firrtl.Port(port, direction) + } + } + + private[core] def setupInParent(implicit sourceInfo: SourceInfo): this.type = { + _parent match { + case Some(p) => { + pushCommand(DefInvalid(sourceInfo, io.ref)) // init instance inputs + clock := override_clock.getOrElse(p.clock) + reset := override_reset.getOrElse(p.reset) + this + } + case None => this + } + } + + private[core] def setRefs(): this.type = { + for ((name, port) <- ports) { + port.setRef(ModuleIO(this, _namespace.name(name))) + } + + // Suggest names to nodes using runtime reflection + def getValNames(c: Class[_]): Set[String] = { + if (c == classOf[Module]) Set() + else getValNames(c.getSuperclass) ++ c.getDeclaredFields.map(_.getName) + } + val valNames = getValNames(this.getClass) + def isPublicVal(m: java.lang.reflect.Method) = + m.getParameterTypes.isEmpty && valNames.contains(m.getName) + + /** Recursively suggests names to supported "container" classes + * Arbitrary nestings of supported classes are allowed so long as the + * innermost element is of type HasId + * Currently supported: + * - Iterable + * - Option + * (Note that Map is Iterable[Tuple2[_,_]] and thus excluded) + */ + def nameRecursively(prefix: String, nameMe: Any): Unit = + nameMe match { + case (id: HasId) => id.suggestName(prefix) + case Some(elt) => nameRecursively(prefix, elt) + case (iter: Iterable[_]) if iter.hasDefiniteSize => + for ((elt, i) <- iter.zipWithIndex) { + nameRecursively(s"${prefix}_${i}", elt) + } + case _ => // Do nothing + } + val methods = getClass.getMethods.sortWith(_.getName > _.getName) + for (m <- methods if isPublicVal(m)) { + nameRecursively(m.getName, m.invoke(this)) + } + + // For Module instances we haven't named, suggest the name of the Module + _ids foreach { + case m: Module => m.suggestName(m.name) + case _ => + } + + // All suggestions are in, force names to every node. + _ids.foreach(_.forceName(default="T", _namespace)) + _ids.foreach(_._onModuleClose) + this + } + // For debuggers/testers + lazy val getPorts = computePorts + val compileOptions = moduleCompileOptions +} diff --git a/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala new file mode 100644 index 00000000..fcb14e6f --- /dev/null +++ b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala @@ -0,0 +1,191 @@ +// See LICENSE for license details. + +package chisel3.core + +import chisel3.internal.Builder.pushCommand +import chisel3.internal.firrtl.Connect +import scala.language.experimental.macros +import chisel3.internal.sourceinfo.{DeprecatedSourceInfo, SourceInfo, SourceInfoTransform, UnlocatableSourceInfo, WireTransform} + +/** +* MonoConnect.connect executes a mono-directional connection element-wise. +* +* Note that this isn't commutative. There is an explicit source and sink +* already determined before this function is called. +* +* The connect operation will recurse down the left Data (with the right Data). +* An exception will be thrown if a movement through the left cannot be matched +* in the right. The right side is allowed to have extra Bundle fields. +* Vecs must still be exactly the same size. +* +* See elemConnect for details on how the root connections are issued. +* +* Note that a valid sink must be writable so, one of these must hold: +* - Is an internal writable node (Reg or Wire) +* - Is an output of the current module +* - Is an input of a submodule of the current module +* +* Note that a valid source must be readable so, one of these must hold: +* - Is an internal readable node (Reg, Wire, Op) +* - Is a literal +* - Is a port of the current module or submodule of the current module +*/ + +object MonoConnect { + // These are all the possible exceptions that can be thrown. + case class MonoConnectException(message: String) extends Exception(message) + // These are from element-level connection + def UnreadableSourceException = + MonoConnectException(": Source is unreadable from current module.") + def UnwritableSinkException = + MonoConnectException(": Sink is unwriteable by current module.") + def UnknownRelationException = + MonoConnectException(": Sink or source unavailable to current module.") + // These are when recursing down aggregate types + def MismatchedVecException = + MonoConnectException(": Sink and Source are different length Vecs.") + def MissingFieldException(field: String) = + MonoConnectException(s": Source Bundle missing field ($field).") + def MismatchedException(sink: String, source: String) = + MonoConnectException(s": Sink ($sink) and Source ($source) have different types.") + + /** This function is what recursively tries to connect a sink and source together + * + * There is some cleverness in the use of internal try-catch to catch exceptions + * during the recursive decent and then rethrow them with extra information added. + * This gives the user a 'path' to where in the connections things went wrong. + */ + def connect(sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, sink: Data, source: Data, context_mod: Module): Unit = + (sink, source) match { + // Handle element case (root case) + case (sink_e: Element, source_e: Element) => { + elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod) + // TODO(twigg): Verify the element-level classes are connectable + } + // Handle Vec case + case (sink_v: Vec[Data @unchecked], source_v: Vec[Data @unchecked]) => { + if(sink_v.length != source_v.length) { throw MismatchedVecException } + for(idx <- 0 until sink_v.length) { + try { + connect(sourceInfo, connectCompileOptions, sink_v(idx), source_v(idx), context_mod) + } catch { + case MonoConnectException(message) => throw MonoConnectException(s"($idx)$message") + } + } + } + // Handle Bundle case + case (sink_b: Bundle, source_b: Bundle) => { + // For each field, descend with right + for((field, sink_sub) <- sink_b.elements) { + try { + source_b.elements.get(field) match { + case Some(source_sub) => connect(sourceInfo, connectCompileOptions, sink_sub, source_sub, context_mod) + case None => { + if (connectCompileOptions.connectFieldsMustMatch) { + throw MissingFieldException(field) + } + } + } + } catch { + case MonoConnectException(message) => throw MonoConnectException(s".$field$message") + } + } + } + // Sink and source are different subtypes of data so fail + case (sink, source) => throw MismatchedException(sink.toString, source.toString) + } + + // This function (finally) issues the connection operation + private def issueConnect(sink: Element, source: Element)(implicit sourceInfo: SourceInfo): Unit = { + pushCommand(Connect(sourceInfo, sink.lref, source.ref)) + } + + // This function checks if element-level connection operation allowed. + // Then it either issues it or throws the appropriate exception. + def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, sink: Element, source: Element, context_mod: Module): Unit = { + import Direction.{Input, Output} // Using extensively so import these + // If source has no location, assume in context module + // This can occur if is a literal, unbound will error previously + val sink_mod: Module = sink.binding.location.getOrElse(throw UnwritableSinkException) + val source_mod: Module = source.binding.location.getOrElse(context_mod) + + val sink_direction: Option[Direction] = sink.binding.direction + val source_direction: Option[Direction] = source.binding.direction + // None means internal + + // CASE: Context is same module that both left node and right node are in + if( (context_mod == sink_mod) && (context_mod == source_mod) ) { + ((sink_direction, source_direction): @unchecked) match { + // SINK SOURCE + // CURRENT MOD CURRENT MOD + case (Some(Output), _) => issueConnect(sink, source) + case (None, _) => issueConnect(sink, source) + case (Some(Input), _) => throw UnwritableSinkException + } + } + + // CASE: Context is same module as sink node and right node is in a child module + else if( (sink_mod == context_mod) && + (source_mod._parent.map(_ == context_mod).getOrElse(false)) ) { + // Thus, right node better be a port node and thus have a direction + ((sink_direction, source_direction): @unchecked) match { + // SINK SOURCE + // CURRENT MOD CHILD MOD + case (None, Some(Output)) => issueConnect(sink, source) + case (None, Some(Input)) => issueConnect(sink, source) + case (Some(Output), Some(Output)) => issueConnect(sink, source) + case (Some(Output), Some(Input)) => issueConnect(sink, source) + case (_, None) => { + if (!(connectCompileOptions.dontAssumeDirectionality)) { + issueConnect(sink, source) + } else { + throw UnreadableSourceException + } + } + case (Some(Input), Some(Output)) if (!(connectCompileOptions.dontTryConnectionsSwapped)) => issueConnect(source, sink) + case (Some(Input), _) => throw UnwritableSinkException + } + } + + // CASE: Context is same module as source node and sink node is in child module + else if( (source_mod == context_mod) && + (sink_mod._parent.map(_ == context_mod).getOrElse(false)) ) { + // Thus, left node better be a port node and thus have a direction + ((sink_direction, source_direction): @unchecked) match { + // SINK SOURCE + // CHILD MOD CURRENT MOD + case (Some(Input), _) => issueConnect(sink, source) + case (Some(Output), _) => throw UnwritableSinkException + case (None, _) => throw UnwritableSinkException + } + } + + // CASE: Context is the parent module of both the module containing sink node + // and the module containing source node + // Note: This includes case when sink and source in same module but in parent + else if( (sink_mod._parent.map(_ == context_mod).getOrElse(false)) && + (source_mod._parent.map(_ == context_mod).getOrElse(false)) + ) { + // Thus both nodes must be ports and have a direction + ((sink_direction, source_direction): @unchecked) match { + // SINK SOURCE + // CHILD MOD CHILD MOD + case (Some(Input), Some(Input)) => issueConnect(sink, source) + case (Some(Input), Some(Output)) => issueConnect(sink, source) + case (Some(Output), _) => throw UnwritableSinkException + case (_, None) => { + if (!(connectCompileOptions.dontAssumeDirectionality)) { + issueConnect(sink, source) + } else { + throw UnreadableSourceException + } + } + case (None, _) => throw UnwritableSinkException + } + } + + // Not quite sure where left and right are compared to current module + // so just error out + else throw UnknownRelationException + } +} diff --git a/chiselFrontend/src/main/scala/chisel3/core/Printable.scala b/chiselFrontend/src/main/scala/chisel3/core/Printable.scala new file mode 100644 index 00000000..f6e63936 --- /dev/null +++ b/chiselFrontend/src/main/scala/chisel3/core/Printable.scala @@ -0,0 +1,152 @@ +// See LICENSE for license details. + +package chisel3.core + +import chisel3.internal.firrtl.Component +import chisel3.internal.HasId + +import scala.collection.mutable + +import java.util.{ + MissingFormatArgumentException, + UnknownFormatConversionException +} + +/** Superclass of things that can be printed in the resulting circuit + * + * Usually created using the custom string interpolator p"..." + * TODO Add support for names of Modules + * Currently impossible because unpack is called before the name is selected + * Could be implemented by adding a new format specifier to Firrtl (eg. %m) + * TODO Should we provide more functions like map and mkPrintable? + */ +sealed abstract class Printable { + /** Unpack into format String and a List of String arguments (identifiers) + * @note This must be called after elaboration when Chisel nodes actually + * have names + */ + def unpack(ctx: Component): (String, Iterable[String]) + /** Allow for appending Printables like Strings */ + final def +(that: Printable) = Printables(List(this, that)) + /** Allow for appending Strings to Printables */ + final def +(that: String) = Printables(List(this, PString(that))) +} +object Printable { + /** Pack standard printf fmt, args* style into Printable + */ + def pack(fmt: String, data: Data*): Printable = { + val args = data.toIterator + + // Error handling + def carrotAt(index: Int) = (" " * index) + "^" + def errorMsg(index: Int) = + s"""| fmt = "$fmt" + | ${carrotAt(index)} + | data = ${data mkString ", "}""".stripMargin + def getArg(i: Int): Data = { + if (!args.hasNext) { + val msg = "has no matching argument!\n" + errorMsg(i) + // Exception wraps msg in s"Format Specifier '$msg'" + throw new MissingFormatArgumentException(msg) + } + args.next() + } + + val pables = mutable.ListBuffer.empty[Printable] + var str = "" + var percent = false + for ((c, i) <- fmt.zipWithIndex) { + if (percent) { + val arg = c match { + case FirrtlFormat(x) => FirrtlFormat(x.toString, getArg(i)) + case 'n' => Name(getArg(i)) + case 'N' => FullName(getArg(i)) + case '%' => Percent + case x => + val msg = s"Illegal format specifier '$x'!\n" + errorMsg(i) + throw new UnknownFormatConversionException(msg) + } + pables += PString(str dropRight 1) // remove format % + pables += arg + str = "" + percent = false + } else { + str += c + percent = c == '%' + } + } + if (percent) { + val msg = s"Trailing %\n" + errorMsg(fmt.size - 1) + throw new UnknownFormatConversionException(msg) + } + require(!args.hasNext, + s"Too many arguments! More format specifier(s) expected!\n" + + errorMsg(fmt.size)) + + pables += PString(str) + Printables(pables) + } +} + +case class Printables(pables: Iterable[Printable]) extends Printable { + require(pables.hasDefiniteSize, "Infinite-sized iterables are not supported!") + final def unpack(ctx: Component): (String, Iterable[String]) = { + val (fmts, args) = pables.map(_ unpack ctx).unzip + (fmts.mkString, args.flatten) + } +} +/** Wrapper for printing Scala Strings */ +case class PString(str: String) extends Printable { + final def unpack(ctx: Component): (String, Iterable[String]) = + (str replaceAll ("%", "%%"), List.empty) +} +/** Superclass for Firrtl format specifiers for Bits */ +sealed abstract class FirrtlFormat(specifier: Char) extends Printable { + def bits: Bits + def unpack(ctx: Component): (String, Iterable[String]) = { + (s"%$specifier", List(bits.ref.fullName(ctx))) + } +} +object FirrtlFormat { + final val legalSpecifiers = List('d', 'x', 'b', 'c') + + def unapply(x: Char): Option[Char] = + Option(x) filter (x => legalSpecifiers contains x) + + /** Helper for constructing Firrtl Formats + * Accepts data to simplify pack + */ + def apply(specifier: String, data: Data): FirrtlFormat = { + val bits = data match { + case b: Bits => b + case d => throw new Exception(s"Trying to construct FirrtlFormat with non-bits $d!") + } + specifier match { + case "d" => Decimal(bits) + case "x" => Hexadecimal(bits) + case "b" => Binary(bits) + case "c" => Character(bits) + case c => throw new Exception(s"Illegal format specifier '$c'!") + } + } +} +/** Format bits as Decimal */ +case class Decimal(bits: Bits) extends FirrtlFormat('d') +/** Format bits as Hexidecimal */ +case class Hexadecimal(bits: Bits) extends FirrtlFormat('x') +/** Format bits as Binary */ +case class Binary(bits: Bits) extends FirrtlFormat('b') +/** Format bits as Character */ +case class Character(bits: Bits) extends FirrtlFormat('c') +/** Put innermost name (eg. field of bundle) */ +case class Name(data: Data) extends Printable { + final def unpack(ctx: Component): (String, Iterable[String]) = (data.ref.name, List.empty) +} +/** Put full name within parent namespace (eg. bundleName.field) */ +case class FullName(data: Data) extends Printable { + final def unpack(ctx: Component): (String, Iterable[String]) = (data.ref.fullName(ctx), List.empty) +} +/** Represents escaped percents */ +case object Percent extends Printable { + final def unpack(ctx: Component): (String, Iterable[String]) = ("%%", List.empty) +} diff --git a/chiselFrontend/src/main/scala/chisel3/core/Printf.scala b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala new file mode 100644 index 00000000..4ec13751 --- /dev/null +++ b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala @@ -0,0 +1,70 @@ +// See LICENSE for license details. + +package chisel3.core + +import scala.language.experimental.macros + +import chisel3.internal._ +import chisel3.internal.Builder.pushCommand +import chisel3.internal.firrtl._ +import chisel3.internal.sourceinfo.SourceInfo + +object printf { // scalastyle:ignore object.name + /** Helper for packing escape characters */ + private[chisel3] def format(formatIn: String): String = { + require(formatIn forall (c => c.toInt > 0 && c.toInt < 128), + "format strings must comprise non-null ASCII values") + def escaped(x: Char) = { + require(x.toInt >= 0) + if (x == '"' || x == '\\') { + s"\\${x}" + } else if (x == '\n') { + "\\n" + } else { + require(x.toInt >= 32) // TODO \xNN once FIRRTL issue #59 is resolved + x + } + } + formatIn map escaped mkString "" + } + + /** Prints a message in simulation. + * + * Does not fire when in reset (defined as the encapsulating Module's + * reset). If your definition of reset is not the encapsulating Module's + * reset, you will need to gate this externally. + * + * May be called outside of a Module (like defined in a function), so + * functions using printf make the standard Module assumptions (single clock + * and single reset). + * + * @param fmt printf format string + * @param data format string varargs containing data to print + */ + def apply(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo): Unit = + apply(Printable.pack(fmt, data:_*)) + /** Prints a message in simulation. + * + * Does not fire when in reset (defined as the encapsulating Module's + * reset). If your definition of reset is not the encapsulating Module's + * reset, you will need to gate this externally. + * + * May be called outside of a Module (like defined in a function), so + * functions using printf make the standard Module assumptions (single clock + * and single reset). + * + * @param pable [[Printable]] to print + */ + def apply(pable: Printable)(implicit sourceInfo: SourceInfo): Unit = { + when (!Builder.forcedModule.reset) { + printfWithoutReset(pable) + } + } + + private[chisel3] def printfWithoutReset(pable: Printable)(implicit sourceInfo: SourceInfo): Unit = { + val clock = Builder.forcedModule.clock + pushCommand(Printf(sourceInfo, Node(clock), pable)) + } + private[chisel3] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo): Unit = + printfWithoutReset(Printable.pack(fmt, data:_*)) +} diff --git a/chiselFrontend/src/main/scala/Chisel/Reg.scala b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala index c8faa5c9..9d380695 100644 --- a/chiselFrontend/src/main/scala/Chisel/Reg.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala @@ -1,22 +1,25 @@ // See LICENSE for license details. -package Chisel +package chisel3.core -import internal._ -import internal.Builder.pushCommand -import internal.firrtl._ -import internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo} +import chisel3.internal._ +import chisel3.internal.Builder.pushCommand +import chisel3.internal.firrtl._ +import chisel3.internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo} object Reg { - private[Chisel] def makeType[T <: Data](t: T = null, next: T = null, init: T = null): T = { + private[core] def makeType[T <: Data](compileOptions: CompileOptions, t: T = null, next: T = null, init: T = null): T = { if (t ne null) { - t.cloneType + if (compileOptions.declaredTypeMustBeUnbound) { + Binding.checkUnbound(t, s"t ($t) must be unbound Type. Try using cloneType?") + } + t.chiselCloneType } else if (next ne null) { next.cloneTypeWidth(Width()) } else if (init ne null) { init.litArg match { // For e.g. Reg(init=UInt(0, k)), fix the Reg's width to k - case Some(lit) if lit.forcedWidth => init.cloneType + case Some(lit) if lit.forcedWidth => init.chiselCloneType case _ => init.cloneTypeWidth(Width()) } } else { @@ -37,18 +40,18 @@ object Reg { * is a valid value. In those cases, you can either use the outType only Reg * constructor or pass in `null.asInstanceOf[T]`. */ - def apply[T <: Data](t: T = null, next: T = null, init: T = null): T = + def apply[T <: Data](t: T = null, next: T = null, init: T = null)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = // Scala macros can't (yet) handle named or default arguments. - do_apply(t, next, init)(UnlocatableSourceInfo) + do_apply(t, next, init)(sourceInfo, compileOptions) /** Creates a register without initialization (reset is ignored). Value does * not change unless assigned to (using the := operator). * * @param outType: data type for the register */ - def apply[T <: Data](outType: T): T = Reg[T](outType, null.asInstanceOf[T], null.asInstanceOf[T]) + def apply[T <: Data](outType: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = Reg[T](outType, null.asInstanceOf[T], null.asInstanceOf[T])(sourceInfo, compileOptions) - def do_apply[T <: Data](t: T, next: T, init: T)(implicit sourceInfo: SourceInfo): T = { + def do_apply[T <: Data](t: T, next: T, init: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions = chisel3.core.ExplicitCompileOptions.NotStrict): T = { // TODO: write this in a way that doesn't need nulls (bad Scala style), // null.asInstanceOf[T], and two constructors. Using Option types are an // option, but introduces cumbersome syntax (wrap everything in a Some()). @@ -56,14 +59,20 @@ object Reg { // but Scala's type inferencer and implicit insertion isn't smart enough // to resolve all use cases. If the type inferencer / implicit resolution // system improves, this may be changed. - val x = makeType(t, next, init) + val x = makeType(compileOptions, t, next, init) val clock = Node(x._parent.get.clock) // TODO multi-clock + + // Bind each element of x to being a Reg + Binding.bind(x, RegBinder(Builder.forcedModule), "Error: t") + if (init == null) { pushCommand(DefReg(sourceInfo, x, clock)) } else { + Binding.checkSynthesizable(init, s"'init' ($init)") pushCommand(DefRegInit(sourceInfo, x, clock, Node(x._parent.get.reset), init.ref)) } if (next != null) { + Binding.checkSynthesizable(next, s"'next' ($next)") x := next } x diff --git a/chiselFrontend/src/main/scala/Chisel/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala index 9a15fd5f..0d8604cd 100644 --- a/chiselFrontend/src/main/scala/Chisel/SeqUtils.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala @@ -1,13 +1,18 @@ // See LICENSE for license details. -package Chisel +package chisel3.core import scala.language.experimental.macros -import internal.sourceinfo.{SourceInfo, SourceInfoTransform} +import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform} -private[Chisel] object SeqUtils { - /** Equivalent to Cat(r(n-1), ..., r(0)) */ +private[chisel3] object SeqUtils { + /** Concatenates the data elements of the input sequence, in sequence order, together. + * The first element of the sequence forms the least significant bits, while the last element + * in the sequence forms the most significant bits. + * + * Equivalent to r(n-1) ## ... ## r(1) ## r(0). + */ def asUInt[T <: Bits](in: Seq[T]): UInt = macro SourceInfoTransform.inArg def do_asUInt[T <: Bits](in: Seq[T])(implicit sourceInfo: SourceInfo): UInt = { @@ -20,20 +25,18 @@ private[Chisel] object SeqUtils { } } - /** Counts the number of true Bools in a Seq */ + /** Outputs the number of elements that === Bool(true). + */ def count(in: Seq[Bool]): UInt = macro SourceInfoTransform.inArg - def do_count(in: Seq[Bool])(implicit sourceInfo: SourceInfo): UInt = { - if (in.size == 0) { - UInt(0) - } else if (in.size == 1) { - in.head - } else { - count(in.slice(0, in.size/2)) + (UInt(0) ## count(in.slice(in.size/2, in.size))) - } + def do_count(in: Seq[Bool])(implicit sourceInfo: SourceInfo): UInt = in.size match { + case 0 => UInt(0) + case 1 => in.head + case n => count(in take n/2) +& count(in drop n/2) } - /** Returns data value corresponding to first true predicate */ + /** Returns the data value corresponding to the first true predicate. + */ def priorityMux[T <: Data](in: Seq[(Bool, T)]): T = macro SourceInfoTransform.inArg def do_priorityMux[T <: Data](in: Seq[(Bool, T)])(implicit sourceInfo: SourceInfo): T = { @@ -44,14 +47,17 @@ private[Chisel] object SeqUtils { } } - /** Returns data value corresponding to lone true predicate */ + /** Returns the data value corresponding to the lone true predicate. + * + * @note assumes exactly one true predicate, results undefined otherwise + */ def oneHotMux[T <: Data](in: Iterable[(Bool, T)]): T = macro SourceInfoTransform.inArg def do_oneHotMux[T <: Data](in: Iterable[(Bool, T)])(implicit sourceInfo: SourceInfo): T = { if (in.tail.isEmpty) { in.head._2 } else { - val masked = for ((s, i) <- in) yield Mux(s, i.toBits, Bits(0)) + val masked = for ((s, i) <- in) yield Mux(s, i.asUInt, UInt(0)) val width = in.map(_._2.width).reduce(_ max _) in.head._2.cloneTypeWidth(width).fromBits(masked.reduceLeft(_|_)) } diff --git a/chiselFrontend/src/main/scala/Chisel/When.scala b/chiselFrontend/src/main/scala/chisel3/core/When.scala index 90b3d1a5..196e7903 100644 --- a/chiselFrontend/src/main/scala/Chisel/When.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/When.scala @@ -1,13 +1,13 @@ // See LICENSE for license details. -package Chisel +package chisel3.core import scala.language.experimental.macros -import internal._ -import internal.Builder.pushCommand -import internal.firrtl._ -import internal.sourceinfo.{SourceInfo} +import chisel3.internal._ +import chisel3.internal.Builder.pushCommand +import chisel3.internal.firrtl._ +import chisel3.internal.sourceinfo.{SourceInfo} object when { // scalastyle:ignore object.name /** Create a `when` condition block, where whether a block of logic is diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala new file mode 100644 index 00000000..12cc840e --- /dev/null +++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala @@ -0,0 +1,190 @@ +// See LICENSE for license details. + +package chisel3.internal + +import scala.util.DynamicVariable +import scala.collection.mutable.{ArrayBuffer, HashMap} + +import chisel3._ +import core._ +import firrtl._ + +private[chisel3] class Namespace(parent: Option[Namespace], keywords: Set[String]) { + private val names = collection.mutable.HashMap[String, Long]() + for (keyword <- keywords) + names(keyword) = 1 + + private def rename(n: String): String = { + val index = names.getOrElse(n, 1L) + val tryName = s"${n}_${index}" + names(n) = index + 1 + if (this contains tryName) rename(n) else tryName + } + + private def sanitize(s: String): String = { + // TODO what character set does FIRRTL truly support? using ANSI C for now + def legalStart(c: Char) = (c >= 'a' && c <= 'z') || (c >= 'A' && c <= 'Z') || c == '_' + def legal(c: Char) = legalStart(c) || (c >= '0' && c <= '9') + val res = s filter legal + if (res.isEmpty || !legalStart(res.head)) s"_$res" else res + } + + def contains(elem: String): Boolean = { + names.contains(elem) || parent.map(_ contains elem).getOrElse(false) + } + + def name(elem: String): String = { + val sanitized = sanitize(elem) + if (this contains sanitized) { + name(rename(sanitized)) + } else { + names(sanitized) = 1 + sanitized + } + } + + def child(kws: Set[String]): Namespace = new Namespace(Some(this), kws) + def child: Namespace = child(Set()) +} + +private[chisel3] class IdGen { + private var counter = -1L + def next: Long = { + counter += 1 + counter + } +} + +/** Public API to access Node/Signal names. + * currently, the node's name, the full path name, and references to its parent Module and component. + * These are only valid once the design has been elaborated, and should not be used during its construction. + */ +trait InstanceId { + def instanceName: String + def pathName: String + def parentPathName: String + def parentModName: String +} + +private[chisel3] trait HasId extends InstanceId { + private[chisel3] def _onModuleClose: Unit = {} // scalastyle:ignore method.name + private[chisel3] val _parent: Option[Module] = Builder.currentModule + _parent.foreach(_.addId(this)) + + private[chisel3] val _id: Long = Builder.idGen.next + override def hashCode: Int = _id.toInt + override def equals(that: Any): Boolean = that match { + case x: HasId => _id == x._id + case _ => false + } + + // Facilities for 'suggesting' a name to this. + // Post-name hooks called to carry the suggestion to other candidates as needed + private var suggested_name: Option[String] = None + private val postname_hooks = scala.collection.mutable.ListBuffer.empty[String=>Unit] + // Only takes the first suggestion! + def suggestName(name: =>String): this.type = { + if(suggested_name.isEmpty) suggested_name = Some(name) + for(hook <- postname_hooks) { hook(name) } + this + } + private[chisel3] def addPostnameHook(hook: String=>Unit): Unit = postname_hooks += hook + + // Uses a namespace to convert suggestion into a true name + // Will not do any naming if the reference already assigned. + // (e.g. tried to suggest a name to part of a Bundle) + private[chisel3] def forceName(default: =>String, namespace: Namespace): Unit = + if(_ref.isEmpty) { + val candidate_name = suggested_name.getOrElse(default) + val available_name = namespace.name(candidate_name) + setRef(Ref(available_name)) + } + + private var _ref: Option[Arg] = None + private[chisel3] def setRef(imm: Arg): Unit = _ref = Some(imm) + private[chisel3] def setRef(parent: HasId, name: String): Unit = setRef(Slot(Node(parent), name)) + private[chisel3] def setRef(parent: HasId, index: Int): Unit = setRef(Index(Node(parent), ILit(index))) + private[chisel3] def setRef(parent: HasId, index: UInt): Unit = setRef(Index(Node(parent), index.ref)) + private[chisel3] def getRef: Arg = _ref.get + + // Implementation of public methods. + def instanceName = _parent match { + case Some(p) => p._component match { + case Some(c) => getRef fullName c + case None => throwException("signalName/pathName should be called after circuit elaboration") + } + case None => throwException("this cannot happen") + } + def pathName = _parent match { + case None => instanceName + case Some(p) => s"${p.pathName}.$instanceName" + } + def parentPathName = _parent match { + case Some(p) => p.pathName + case None => throwException(s"$instanceName doesn't have a parent") + } + def parentModName = _parent match { + case Some(p) => p.modName + case None => throwException(s"$instanceName doesn't have a parent") + } +} + +private[chisel3] class DynamicContext() { + val idGen = new IdGen + val globalNamespace = new Namespace(None, Set()) + val components = ArrayBuffer[Component]() + var currentModule: Option[Module] = None + val errors = new ErrorLog +} + +private[chisel3] object Builder { + // All global mutable state must be referenced via dynamicContextVar!! + private val dynamicContextVar = new DynamicVariable[Option[DynamicContext]](None) + private def dynamicContext: DynamicContext = + dynamicContextVar.value.getOrElse(new DynamicContext) + + def idGen: IdGen = dynamicContext.idGen + def globalNamespace: Namespace = dynamicContext.globalNamespace + def components: ArrayBuffer[Component] = dynamicContext.components + + def currentModule: Option[Module] = dynamicContext.currentModule + def currentModule_=(target: Option[Module]): Unit = { + dynamicContext.currentModule = target + } + def forcedModule: Module = currentModule match { + case Some(module) => module + case None => throw new Exception( + "Error: Not in a Module. Likely cause: Missed Module() wrap or bare chisel API call." + // A bare api call is, e.g. calling Wire() from the scala console). + ) + } + + // TODO(twigg): Ideally, binding checks and new bindings would all occur here + // However, rest of frontend can't support this yet. + def pushCommand[T <: Command](c: T): T = { + forcedModule._commands += c + c + } + def pushOp[T <: Data](cmd: DefPrim[T]): T = { + // Bind each element of the returned Data to being a Op + Binding.bind(cmd.id, OpBinder(forcedModule), "Error: During op creation, fresh result") + pushCommand(cmd).id + } + + def errors: ErrorLog = dynamicContext.errors + def error(m: => String): Unit = errors.error(m) + def warning(m: => String): Unit = errors.warning(m) + def deprecated(m: => String): Unit = errors.deprecated(m) + + def build[T <: Module](f: => T): Circuit = { + dynamicContextVar.withValue(Some(new DynamicContext())) { + errors.info("Elaborating design...") + val mod = f + mod.forceName(mod.name, globalNamespace) + errors.checkpoint() + errors.info("Done elaborating.") + + Circuit(components.last.name, components) + } + } +} diff --git a/chiselFrontend/src/main/scala/Chisel/internal/Error.scala b/chiselFrontend/src/main/scala/chisel3/internal/Error.scala index 6c4c0880..c5c67da4 100644 --- a/chiselFrontend/src/main/scala/Chisel/internal/Error.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/Error.scala @@ -1,20 +1,20 @@ // See LICENSE for license details. -package Chisel.internal +package chisel3.internal import scala.collection.mutable.ArrayBuffer -import Chisel._ +import chisel3.core._ class ChiselException(message: String, cause: Throwable) extends Exception(message, cause) -private[Chisel] object throwException { +private[chisel3] object throwException { def apply(s: String, t: Throwable = null): Nothing = throw new ChiselException(s, t) } /** Records and reports runtime errors and warnings. */ -private[Chisel] class ErrorLog { +private[chisel3] class ErrorLog { def hasErrors: Boolean = errors.exists(_.isFatal) /** Log an error message */ @@ -25,6 +25,10 @@ private[Chisel] class ErrorLog { def warning(m: => String): Unit = errors += new Warning(m, getUserLineNumber) + /** Log a deprecation warning message */ + def deprecated(m: => String): Unit = + errors += new DeprecationWarning(m, getUserLineNumber) + /** Emit an informational message */ def info(m: String): Unit = println(new Info("[%2.3f] %s".format(elapsedTime/1e3, m), None)) // scalastyle:ignore regex @@ -86,6 +90,10 @@ private class Warning(msg: => String, line: Option[StackTraceElement]) extends L def format: String = tag("warn", Console.YELLOW) } +private class DeprecationWarning(msg: => String, line: Option[StackTraceElement]) extends LogEntry(msg, line) { + def format: String = tag("warn", Console.CYAN) +} + private class Info(msg: => String, line: Option[StackTraceElement]) extends LogEntry(msg, line) { def format: String = tag("info", Console.MAGENTA) } diff --git a/chiselFrontend/src/main/scala/Chisel/internal/SourceInfo.scala b/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala index 66bfc7a4..5e3bf33e 100644 --- a/chiselFrontend/src/main/scala/Chisel/internal/SourceInfo.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala @@ -12,7 +12,7 @@ // writers to append source locator information at the point of a library // function invocation. -package Chisel.internal.sourceinfo +package chisel3.internal.sourceinfo import scala.language.experimental.macros import scala.reflect.macros.blackbox.Context @@ -42,7 +42,7 @@ object SourceInfoMacro { def generate_source_info(c: Context): c.Tree = { import c.universe._ val p = c.enclosingPosition - q"_root_.Chisel.internal.sourceinfo.SourceLine(${p.source.file.name}, ${p.line}, ${p.column})" + q"_root_.chisel3.internal.sourceinfo.SourceLine(${p.source.file.name}, ${p.line}, ${p.column})" } } diff --git a/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index 62784cee..0641686c 100644 --- a/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -1,9 +1,11 @@ // See LICENSE for license details. -package Chisel.internal.firrtl -import Chisel._ -import Chisel.internal._ -import Chisel.internal.sourceinfo.{SourceInfo, NoSourceInfo} +package chisel3.internal.firrtl + +import chisel3._ +import core._ +import chisel3.internal._ +import chisel3.internal.sourceinfo.{SourceInfo, NoSourceInfo} case class PrimOp(val name: String) { override def toString: String = name @@ -40,6 +42,7 @@ object PrimOp { val ConvertOp = PrimOp("cvt") val AsUIntOp = PrimOp("asUInt") val AsSIntOp = PrimOp("asSInt") + val AsClockOp = PrimOp("asClock") } abstract class Arg { @@ -53,8 +56,8 @@ case class Node(id: HasId) extends Arg { } abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg { - private[Chisel] def forcedWidth = widthArg.known - private[Chisel] def width: Width = if (forcedWidth) widthArg else Width(minWidth) + private[chisel3] def forcedWidth = widthArg.known + private[chisel3] def width: Width = if (forcedWidth) widthArg else Width(minWidth) protected def minWidth: Int if (forcedWidth) { @@ -164,25 +167,9 @@ case class WhenEnd(sourceInfo: SourceInfo) extends Command case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command -case class Stop(sourceInfo: SourceInfo, clk: Arg, ret: Int) extends Command +case class Stop(sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Command case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Arg case class Port(id: Data, dir: Direction) -case class Printf(sourceInfo: SourceInfo, clk: Arg, formatIn: String, ids: Seq[Arg]) extends Command { - require(formatIn.forall(c => c.toInt > 0 && c.toInt < 128), "format strings must comprise non-null ASCII values") - def format: String = { - def escaped(x: Char) = { - require(x.toInt >= 0) - if (x == '"' || x == '\\') { - s"\\${x}" - } else if (x == '\n') { - "\\n" - } else { - require(x.toInt >= 32) // TODO \xNN once FIRRTL issue #59 is resolved - x - } - } - formatIn.map(escaped _).mkString - } -} +case class Printf(sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Command case class Circuit(name: String, components: Seq[Component]) diff --git a/coreMacros/src/main/scala/Chisel/internal/sourceinfo/SourceInfoTransform.scala b/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala index 82ad5b9e..ba14b78f 100644 --- a/coreMacros/src/main/scala/Chisel/internal/sourceinfo/SourceInfoTransform.scala +++ b/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala @@ -3,7 +3,7 @@ // This file transform macro definitions to explicitly add implicit source info to Chisel method // calls. -package Chisel.internal.sourceinfo +package chisel3.internal.sourceinfo import scala.language.experimental.macros import scala.reflect.macros.blackbox.Context @@ -23,7 +23,7 @@ trait SourceInfoTransformMacro { val c: Context import c.universe._ def thisObj = c.prefix.tree - def implicitSourceInfo = q"implicitly[_root_.Chisel.internal.sourceinfo.SourceInfo]" + def implicitSourceInfo = q"implicitly[_root_.chisel3.internal.sourceinfo.SourceInfo]" } class WireTransform(val c: Context) extends SourceInfoTransformMacro { diff --git a/project/plugins.sbt b/project/plugins.sbt index 585435a0..58166621 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -13,3 +13,5 @@ addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.3.5") addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.5.4") addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "0.8.2") + +addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.3.3") diff --git a/src/main/resources/top.cpp b/src/main/resources/top.cpp index 8bfe2a99..075d7085 100644 --- a/src/main/resources/top.cpp +++ b/src/main/resources/top.cpp @@ -44,10 +44,10 @@ int main(int argc, char** argv) { top->reset = 0; // Deassert reset } if ((main_time % 10) == 1) { - top->clk = 1; // Toggle clock + top->clock = 1; // Toggle clock } if ((main_time % 10) == 6) { - top->clk = 0; + top->clock = 0; } top->eval(); // Evaluate model #if VM_TRACE @@ -69,10 +69,10 @@ int main(int argc, char** argv) { vluint64_t end_time = main_time + 100; while (main_time < end_time) { if ((main_time % 10) == 1) { - top->clk = 1; // Toggle clock + top->clock = 1; // Toggle clock } if ((main_time % 10) == 6) { - top->clk = 0; + top->clock = 0; } top->eval(); // Evaluate model #if VM_TRACE diff --git a/src/main/scala/Chisel/FileSystemUtilities.scala b/src/main/scala/Chisel/FileSystemUtilities.scala deleted file mode 100644 index 575ae138..00000000 --- a/src/main/scala/Chisel/FileSystemUtilities.scala +++ /dev/null @@ -1,10 +0,0 @@ -// See LICENSE for license details. - -package Chisel - -@deprecated("FileSystemUtilities doesn't exist in chisel3", "3.0.0") -trait FileSystemUtilities { - def createOutputFile(name: String): java.io.FileWriter = { - new java.io.FileWriter(Driver.targetDir + "/" + name) - } -} diff --git a/src/main/scala/Chisel/package.scala b/src/main/scala/Chisel/package.scala deleted file mode 100644 index f05e8b5d..00000000 --- a/src/main/scala/Chisel/package.scala +++ /dev/null @@ -1,31 +0,0 @@ -package object Chisel { - import scala.language.experimental.macros - - import internal.firrtl.Width - import internal.sourceinfo.{SourceInfo, SourceInfoTransform} - - implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal { - def U: UInt = UInt(x, Width()) - def S: SInt = SInt(x, Width()) - } - implicit class fromIntToLiteral(val x: Int) extends AnyVal { - def U: UInt = UInt(BigInt(x), Width()) - def S: SInt = SInt(BigInt(x), Width()) - } - implicit class fromStringToLiteral(val x: String) extends AnyVal { - def U: UInt = UInt(x) - } - implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal { - def B: Bool = Bool(x) - } - - implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal { - final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg - final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg - final def =/= (that: BitPat): Bool = macro SourceInfoTransform.thatArg - - def do_=== (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that === x - def do_!= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that != x - def do_=/= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that =/= x - } -} diff --git a/src/main/scala/Chisel/util/Cat.scala b/src/main/scala/Chisel/util/Cat.scala deleted file mode 100644 index dd706e62..00000000 --- a/src/main/scala/Chisel/util/Cat.scala +++ /dev/null @@ -1,18 +0,0 @@ -// See LICENSE for license details. - -package Chisel - -object Cat { - /** Combine data elements together - * @param a Data to combine with - * @param r any number of other Data elements to be combined in order - * @return A UInt which is all of the bits combined together - */ - def apply[T <: Bits](a: T, r: T*): UInt = apply(a :: r.toList) - - /** Combine data elements together - * @param r any number of other Data elements to be combined in order - * @return A UInt which is all of the bits combined together - */ - def apply[T <: Bits](r: Seq[T]): UInt = SeqUtils.asUInt(r.reverse) -} diff --git a/src/main/scala/Chisel/util/CircuitMath.scala b/src/main/scala/Chisel/util/CircuitMath.scala deleted file mode 100644 index 06cab903..00000000 --- a/src/main/scala/Chisel/util/CircuitMath.scala +++ /dev/null @@ -1,26 +0,0 @@ -// See LICENSE for license details. - -/** Circuit-land math operations. - */ - -package Chisel - -/** Compute Log2 with truncation of a UInt in hardware using a Mux Tree - * An alternative interpretation is it computes the minimum number of bits needed to represent x - * @example - * {{{ data_out := Log2(data_in) }}} - * @note Truncation is used so Log2(UInt(12412)) = 13*/ -object Log2 { - /** Compute the Log2 on the least significant n bits of x */ - def apply(x: Bits, width: Int): UInt = { - if (width < 2) { - UInt(0) - } else if (width == 2) { - x(1) - } else { - Mux(x(width-1), UInt(width-1), apply(x, width-1)) - } - } - - def apply(x: Bits): UInt = apply(x, x.getWidth) -} diff --git a/src/main/scala/Chisel/util/Conditional.scala b/src/main/scala/Chisel/util/Conditional.scala deleted file mode 100644 index 9cab25ef..00000000 --- a/src/main/scala/Chisel/util/Conditional.scala +++ /dev/null @@ -1,69 +0,0 @@ -// See LICENSE for license details. - -/** Conditional blocks. - */ - -package Chisel - -import scala.language.reflectiveCalls -import scala.language.experimental.macros -import scala.reflect.runtime.universe._ -import scala.reflect.macros.blackbox._ - -/** This is identical to [[Chisel.when when]] with the condition inverted */ -object unless { // scalastyle:ignore object.name - def apply(c: Bool)(block: => Unit) { - when (!c) { block } - } -} - -class SwitchContext[T <: Bits](cond: T) { - def is(v: Iterable[T])(block: => Unit) { - if (!v.isEmpty) when (v.map(_.asUInt === cond.asUInt).reduce(_||_)) { block } - } - def is(v: T)(block: => Unit) { is(Seq(v))(block) } - def is(v: T, vr: T*)(block: => Unit) { is(v :: vr.toList)(block) } -} - -/** An object for separate cases in [[Chisel.switch switch]] - * It is equivalent to a [[Chisel.when$ when]] block comparing to the condition - * Use outside of a switch statement is illegal */ -object is { // scalastyle:ignore object.name - // Begin deprecation of non-type-parameterized is statements. - def apply(v: Iterable[Bits])(block: => Unit) { - require(false, "The 'is' keyword may not be used outside of a switch.") - } - - def apply(v: Bits)(block: => Unit) { - require(false, "The 'is' keyword may not be used outside of a switch.") - } - - def apply(v: Bits, vr: Bits*)(block: => Unit) { - require(false, "The 'is' keyword may not be used outside of a switch.") - } -} - -/** Conditional logic to form a switch block - * @example - * {{{ ... // default values here - * switch ( myState ) { - * is( state1 ) { - * ... // some logic here - * } - * is( state2 ) { - * ... // some logic here - * } - * } }}}*/ -object switch { // scalastyle:ignore object.name - def apply[T <: Bits](cond: T)(x: => Unit): Unit = macro impl - def impl(c: Context)(cond: c.Tree)(x: c.Tree): c.Tree = { import c.universe._ - val sc = c.universe.internal.reificationSupport.freshTermName("sc") - def extractIsStatement(tree: Tree): List[c.universe.Tree] = tree match { - case q"Chisel.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )") - case b => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.") - } - val q"..$body" = x - val ises = body.flatMap(extractIsStatement(_)) - q"""{ val $sc = new SwitchContext($cond); ..$ises }""" - } -} diff --git a/src/main/scala/Chisel/util/Decoupled.scala b/src/main/scala/Chisel/util/Decoupled.scala deleted file mode 100644 index 8e045855..00000000 --- a/src/main/scala/Chisel/util/Decoupled.scala +++ /dev/null @@ -1,183 +0,0 @@ -// See LICENSE for license details. - -/** Wrappers for ready-valid (Decoupled) interfaces and associated circuit generators using them. - */ - -package Chisel - -/** An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'*/ -class DecoupledIO[+T <: Data](gen: T) extends Bundle -{ - val ready = Bool(INPUT) - val valid = Bool(OUTPUT) - val bits = gen.cloneType.asOutput - def fire(dummy: Int = 0): Bool = ready && valid - override def cloneType: this.type = new DecoupledIO(gen).asInstanceOf[this.type] -} - -/** Adds a ready-valid handshaking protocol to any interface. - * The standard used is that the consumer uses the flipped interface. - */ -object Decoupled { - def apply[T <: Data](gen: T): DecoupledIO[T] = new DecoupledIO(gen) -} - -/** An I/O bundle for enqueuing data with valid/ready handshaking - * Initialization must be handled, if necessary, by the parent circuit - */ -class EnqIO[T <: Data](gen: T) extends DecoupledIO(gen) -{ - /** push dat onto the output bits of this interface to let the consumer know it has happened. - * @param dat the values to assign to bits. - * @return dat. - */ - def enq(dat: T): T = { valid := Bool(true); bits := dat; dat } - - /** Initialize this Bundle. Valid is set to false, and all bits are set to zero. - * NOTE: This method of initialization is still being discussed and could change in the - * future. - */ - def init(): Unit = { - valid := Bool(false) - for (io <- bits.flatten) - io := UInt(0) - } - override def cloneType: this.type = { new EnqIO(gen).asInstanceOf[this.type]; } -} - -/** An I/O bundle for dequeuing data with valid/ready handshaking. - * Initialization must be handled, if necessary, by the parent circuit - */ -class DeqIO[T <: Data](gen: T) extends DecoupledIO(gen) with Flipped -{ - /** Assert ready on this port and return the associated data bits. - * This is typically used when valid has been asserted by the producer side. - * @param b ignored - * @return the data for this device, - */ - def deq(b: Boolean = false): T = { ready := Bool(true); bits } - - /** Initialize this Bundle. - * NOTE: This method of initialization is still being discussed and could change in the - * future. - */ - def init(): Unit = { - ready := Bool(false) - } - override def cloneType: this.type = { new DeqIO(gen).asInstanceOf[this.type]; } -} - -/** An I/O bundle for dequeuing data with valid/ready handshaking */ -class DecoupledIOC[+T <: Data](gen: T) extends Bundle -{ - val ready = Bool(INPUT) - val valid = Bool(OUTPUT) - val bits = gen.cloneType.asOutput -} - -/** An I/O Bundle for Queues - * @param gen The type of data to queue - * @param entries The max number of entries in the queue */ -class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle -{ - /** I/O to enqueue data, is [[Chisel.DecoupledIO]] flipped */ - val enq = Decoupled(gen.cloneType).flip() - /** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/ - val deq = Decoupled(gen.cloneType) - /** The current amount of data in the queue */ - val count = UInt(OUTPUT, log2Up(entries + 1)) -} - -/** A hardware module implementing a Queue - * @param gen The type of data to queue - * @param entries The max number of entries in the queue - * @param pipe True if a single entry queue can run at full throughput (like a pipeline). The ''ready'' signals are - * combinationally coupled. - * @param flow True if the inputs can be consumed on the same cycle (the inputs "flow" through the queue immediately). - * The ''valid'' signals are coupled. - * - * Example usage: - * {{{ val q = new Queue(UInt(), 16) - * q.io.enq <> producer.io.out - * consumer.io.in <> q.io.deq }}} - */ -class Queue[T <: Data](gen: T, val entries: Int, - pipe: Boolean = false, - flow: Boolean = false, - override_reset: Option[Bool] = None) -extends Module(override_reset=override_reset) { - def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, _reset: Bool) = - this(gen, entries, pipe, flow, Some(_reset)) - - val io = new QueueIO(gen, entries) - - val ram = Mem(entries, gen) - val enq_ptr = Counter(entries) - val deq_ptr = Counter(entries) - val maybe_full = Reg(init=Bool(false)) - - val ptr_match = enq_ptr.value === deq_ptr.value - val empty = ptr_match && !maybe_full - val full = ptr_match && maybe_full - val do_enq = Wire(init=io.enq.fire()) - val do_deq = Wire(init=io.deq.fire()) - - when (do_enq) { - ram(enq_ptr.value) := io.enq.bits - enq_ptr.inc() - } - when (do_deq) { - deq_ptr.inc() - } - when (do_enq != do_deq) { - maybe_full := do_enq - } - - io.deq.valid := !empty - io.enq.ready := !full - io.deq.bits := ram(deq_ptr.value) - - if (flow) { - when (io.enq.valid) { io.deq.valid := Bool(true) } - when (empty) { - io.deq.bits := io.enq.bits - do_deq := Bool(false) - when (io.deq.ready) { do_enq := Bool(false) } - } - } - - if (pipe) { - when (io.deq.ready) { io.enq.ready := Bool(true) } - } - - val ptr_diff = enq_ptr.value - deq_ptr.value - if (isPow2(entries)) { - io.count := Cat(maybe_full && ptr_match, ptr_diff) - } else { - io.count := Mux(ptr_match, - Mux(maybe_full, - UInt(entries), UInt(0)), - Mux(deq_ptr.value > enq_ptr.value, - UInt(entries) + ptr_diff, ptr_diff)) - } -} - -/** Generic hardware queue. Required parameter entries controls - the depth of the queues. The width of the queue is determined - from the inputs. - - Example usage: - {{{ val q = Queue(Decoupled(UInt()), 16) - q.io.enq <> producer.io.out - consumer.io.in <> q.io.deq }}} - */ -object Queue -{ - def apply[T <: Data](enq: DecoupledIO[T], entries: Int = 2, pipe: Boolean = false): DecoupledIO[T] = { - val q = Module(new Queue(enq.bits.cloneType, entries, pipe)) - q.io.enq.valid := enq.valid // not using <> so that override is allowed - q.io.enq.bits := enq.bits - enq.ready := q.io.enq.ready - TransitName(q.io.deq, q) - } -} diff --git a/src/main/scala/Chisel/util/Enum.scala b/src/main/scala/Chisel/util/Enum.scala deleted file mode 100644 index 20057197..00000000 --- a/src/main/scala/Chisel/util/Enum.scala +++ /dev/null @@ -1,21 +0,0 @@ -// See LICENSE for license details. - -/** Enum generators, allowing circuit constants to have more meaningful names. - */ - -package Chisel - -object Enum { - /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */ - private def createValues[T <: Bits](nodeType: T, n: Int): Seq[T] = - (0 until n).map(x => nodeType.fromInt(x, log2Up(n))) - - /** create n enum values of given type */ - def apply[T <: Bits](nodeType: T, n: Int): List[T] = createValues(nodeType, n).toList - - /** create enum values of given type and names */ - def apply[T <: Bits](nodeType: T, l: Symbol *): Map[Symbol, T] = (l zip createValues(nodeType, l.length)).toMap - - /** create enum values of given type and names */ - def apply[T <: Bits](nodeType: T, l: List[Symbol]): Map[Symbol, T] = (l zip createValues(nodeType, l.length)).toMap -} diff --git a/src/main/scala/Chisel/util/LFSR.scala b/src/main/scala/Chisel/util/LFSR.scala deleted file mode 100644 index 839b1d1f..00000000 --- a/src/main/scala/Chisel/util/LFSR.scala +++ /dev/null @@ -1,22 +0,0 @@ -// See LICENSE for license details. - -/** LFSRs in all shapes and sizes. - */ - -package Chisel - -// scalastyle:off magic.number -/** linear feedback shift register - */ -object LFSR16 -{ - def apply(increment: Bool = Bool(true)): UInt = - { - val width = 16 - val lfsr = Reg(init=UInt(1, width)) - when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) } - lfsr - } -} -// scalastyle:on magic.number - diff --git a/src/main/scala/Chisel/util/Reg.scala b/src/main/scala/Chisel/util/Reg.scala deleted file mode 100644 index 6584a4bf..00000000 --- a/src/main/scala/Chisel/util/Reg.scala +++ /dev/null @@ -1,55 +0,0 @@ -// See LICENSE for license details. - -/** Variations and helpers for registers. - */ - -package Chisel - -object RegNext { - - def apply[T <: Data](next: T): T = Reg[T](null.asInstanceOf[T], next, null.asInstanceOf[T]) - - def apply[T <: Data](next: T, init: T): T = Reg[T](null.asInstanceOf[T], next, init) - -} - -object RegInit { - - def apply[T <: Data](init: T): T = Reg[T](null.asInstanceOf[T], null.asInstanceOf[T], init) - -} - -/** A register with an Enable signal */ -object RegEnable -{ - def apply[T <: Data](updateData: T, enable: Bool): T = { - val r = Reg(updateData) - when (enable) { r := updateData } - r - } - def apply[T <: Data](updateData: T, resetData: T, enable: Bool): T = { - val r = RegInit(resetData) - when (enable) { r := updateData } - r - } -} - -/** Returns the n-cycle delayed version of the input signal. - */ -object ShiftRegister -{ - /** @param in input to delay - * @param n number of cycles to delay - * @param en enable the shift */ - def apply[T <: Data](in: T, n: Int, en: Bool = Bool(true)): T = - { - // The order of tests reflects the expected use cases. - if (n == 1) { - RegEnable(in, en) - } else if (n != 0) { - RegNext(apply(in, n-1, en)) - } else { - in - } - } -} diff --git a/src/main/scala/Chisel/util/TransitName.scala b/src/main/scala/Chisel/util/TransitName.scala deleted file mode 100644 index ec5a11cc..00000000 --- a/src/main/scala/Chisel/util/TransitName.scala +++ /dev/null @@ -1,21 +0,0 @@ -package Chisel - -import internal.HasId - -object TransitName { - // The purpose of this is to allow a library to 'move' a name call to a more - // appropriate place. - // For example, a library factory function may create a module and return - // the io. The only user-exposed field is that given IO, which can't use - // any name supplied by the user. This can add a hook so that the supplied - // name then names the Module. - // See Queue companion object for working example - def apply[T<:HasId](from: T, to: HasId): T = { - from.addPostnameHook((given_name: String) => {to.suggestName(given_name)}) - from - } - def withSuffix[T<:HasId](suffix: String)(from: T, to: HasId): T = { - from.addPostnameHook((given_name: String) => {to.suggestName(given_name+suffix)}) - from - } -} diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/chisel3/Driver.scala index 02204684..5e0a3a0f 100644 --- a/src/main/scala/Chisel/Driver.scala +++ b/src/main/scala/chisel3/Driver.scala @@ -1,6 +1,6 @@ // See LICENSE for license details. -package Chisel +package chisel3 import scala.sys.process._ import java.io._ @@ -47,7 +47,7 @@ trait BackendCompilationUtilities { * C++ sources and headers as well as a makefile to compile them. * * @param dutFile name of the DUT .v without the .v extension - * @param name of the top-level module in the design + * @param topModule of the top-level module in the design * @param dir output directory * @param vSources list of additional Verilog sources to compile * @param cppHarness C++ testharness to compile/link against @@ -71,6 +71,7 @@ trait BackendCompilationUtilities { "--top-module", topModule, "+define+TOP_TYPE=V" + dutFile, s"+define+PRINTF_COND=!$topModule.reset", + s"+define+STOP_COND=!$topModule.reset", "-CFLAGS", s"""-Wno-undefined-bool-conversion -O2 -DTOP_TYPE=V$dutFile -include V$dutFile.h""", "-Mdir", dir.toString, @@ -111,6 +112,8 @@ object Driver extends BackendCompilationUtilities { def emit[T <: Module](gen: () => T): String = Emitter.emit(elaborate(gen)) + def emit[T <: Module](ir: Circuit): String = Emitter.emit(ir) + def dumpFirrtl(ir: Circuit, optName: Option[File]): File = { val f = optName.getOrElse(new File(ir.name + ".fir")) val w = new FileWriter(f) diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala new file mode 100644 index 00000000..d13fcb06 --- /dev/null +++ b/src/main/scala/chisel3/compatibility.scala @@ -0,0 +1,211 @@ +// See LICENSE for license details. + +// Allows legacy users to continue using Chisel (capital C) package name while +// moving to the more standard package naming convention chisel3 (lowercase c). + +package object Chisel { // scalastyle:ignore package.object.name + implicit val defaultCompileOptions = chisel3.core.ExplicitCompileOptions.NotStrict + type Direction = chisel3.core.Direction + val INPUT = chisel3.core.Direction.Input + val OUTPUT = chisel3.core.Direction.Output + val NODIR = chisel3.core.Direction.Unspecified + object Flipped { + def apply[T<:Data](target: T): T = chisel3.core.Flipped[T](target) + } + // TODO: Possibly move the AddDirectionToData class here? + implicit class AddDirMethodToData[T<:Data](val target: T) extends AnyVal { + def dir: Direction = { + target match { + case e: Element => e.dir + case _ => chisel3.core.Direction.Unspecified + } + } + } + + type ChiselException = chisel3.internal.ChiselException + + type Data = chisel3.core.Data + val Wire = chisel3.core.Wire + val Clock = chisel3.core.Clock + type Clock = chisel3.core.Clock + + type Aggregate = chisel3.core.Aggregate + val Vec = chisel3.core.Vec + type Vec[T <: Data] = chisel3.core.Vec[T] + type VecLike[T <: Data] = chisel3.core.VecLike[T] + type Bundle = chisel3.core.Bundle + + val assert = chisel3.core.assert + val stop = chisel3.core.stop + + type Element = chisel3.core.Element + type Bits = chisel3.core.Bits + val Bits = chisel3.core.Bits + type Num[T <: Data] = chisel3.core.Num[T] + type UInt = chisel3.core.UInt + val UInt = chisel3.core.UInt + type SInt = chisel3.core.SInt + val SInt = chisel3.core.SInt + type Bool = chisel3.core.Bool + val Bool = chisel3.core.Bool + val Mux = chisel3.core.Mux + + type BlackBox = chisel3.core.BlackBox + + val Mem = chisel3.core.Mem + type MemBase[T <: Data] = chisel3.core.MemBase[T] + type Mem[T <: Data] = chisel3.core.Mem[T] + val SeqMem = chisel3.core.SeqMem + type SeqMem[T <: Data] = chisel3.core.SeqMem[T] + + val Module = chisel3.core.Module + type Module = chisel3.core.Module + + val printf = chisel3.core.printf + + val Reg = chisel3.core.Reg + + val when = chisel3.core.when + type WhenContext = chisel3.core.WhenContext + + import chisel3.internal.firrtl.Width + /** + * These implicit classes allow one to convert scala.Int|scala.BigInt to + * Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively. + * The versions .asUInt(width)|.asSInt(width) are also available to explicitly + * mark a width for the new literal. + * + * Also provides .asBool to scala.Boolean and .asUInt to String + * + * Note that, for stylistic reasons, one should avoid extracting immediately + * after this call using apply, ie. 0.asUInt(1)(0) due to potential for + * confusion (the 1 is a bit length and the 0 is a bit extraction position). + * Prefer storing the result and then extracting from it. + */ + implicit class fromIntToLiteral(val x: Int) extends AnyVal { + def U: UInt = UInt(BigInt(x), Width()) // scalastyle:ignore method.name + def S: SInt = SInt(BigInt(x), Width()) // scalastyle:ignore method.name + + def asUInt(): UInt = UInt(x, Width()) + def asSInt(): SInt = SInt(x, Width()) + def asUInt(width: Int): UInt = UInt(x, width) + def asSInt(width: Int): SInt = SInt(x, width) + } + + implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal { + def U: UInt = UInt(x, Width()) // scalastyle:ignore method.name + def S: SInt = SInt(x, Width()) // scalastyle:ignore method.name + + def asUInt(): UInt = UInt(x, Width()) + def asSInt(): SInt = SInt(x, Width()) + def asUInt(width: Int): UInt = UInt(x, width) + def asSInt(width: Int): SInt = SInt(x, width) + } + implicit class fromStringToLiteral(val x: String) extends AnyVal { + def U: UInt = UInt(x) // scalastyle:ignore method.name + } + implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal { + def B: Bool = Bool(x) // scalastyle:ignore method.name + } + + + type BackendCompilationUtilities = chisel3.BackendCompilationUtilities + val Driver = chisel3.Driver + val ImplicitConversions = chisel3.util.ImplicitConversions + val chiselMain = chisel3.compatibility.chiselMain + val throwException = chisel3.compatibility.throwException + val debug = chisel3.compatibility.debug + + object testers { // scalastyle:ignore object.name + type BasicTester = chisel3.testers.BasicTester + val TesterDriver = chisel3.testers.TesterDriver + } + + + val log2Up = chisel3.util.log2Up + val log2Ceil = chisel3.util.log2Ceil + val log2Down = chisel3.util.log2Down + val log2Floor = chisel3.util.log2Floor + val isPow2 = chisel3.util.isPow2 + + val BitPat = chisel3.util.BitPat + type BitPat = chisel3.util.BitPat + + type ArbiterIO[T <: Data] = chisel3.util.ArbiterIO[T] + type LockingArbiterLike[T <: Data] = chisel3.util.LockingArbiterLike[T] + type LockingRRArbiter[T <: Data] = chisel3.util.LockingRRArbiter[T] + type LockingArbiter[T <: Data] = chisel3.util.LockingArbiter[T] + type RRArbiter[T <: Data] = chisel3.util.RRArbiter[T] + type Arbiter[T <: Data] = chisel3.util.Arbiter[T] + + val FillInterleaved = chisel3.util.FillInterleaved + val PopCount = chisel3.util.PopCount + val Fill = chisel3.util.Fill + val Reverse = chisel3.util.Reverse + + val Cat = chisel3.util.Cat + + val Log2 = chisel3.util.Log2 + + val unless = chisel3.util.unless + type SwitchContext[T <: Bits] = chisel3.util.SwitchContext[T] + val is = chisel3.util.is + val switch = chisel3.util.switch + + type Counter = chisel3.util.Counter + val Counter = chisel3.util.Counter + + type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T] + val DecoupledIO = chisel3.util.Decoupled + val Decoupled = chisel3.util.Decoupled + class EnqIO[+T <: Data](gen: T) extends DecoupledIO(gen) { + def init(): Unit = { + this.noenq() + } + override def cloneType: this.type = EnqIO(gen).asInstanceOf[this.type] + } + class DeqIO[+T <: Data](gen: T) extends DecoupledIO(gen) { + chisel3.core.Binding.bind(this, chisel3.core.FlippedBinder, "Error: Cannot flip ") + def init(): Unit = { + this.nodeq() + } + override def cloneType: this.type = DeqIO(gen).asInstanceOf[this.type] + } + object EnqIO { + def apply[T<:Data](gen: T): DecoupledIO[T] = DecoupledIO(gen) + } + object DeqIO { + def apply[T<:Data](gen: T): DecoupledIO[T] = Flipped(DecoupledIO(gen)) + } + type QueueIO[T <: Data] = chisel3.util.QueueIO[T] + type Queue[T <: Data] = chisel3.util.Queue[T] + val Queue = chisel3.util.Queue + + val Enum = chisel3.util.Enum + + val LFSR16 = chisel3.util.LFSR16 + + val ListLookup = chisel3.util.ListLookup + val Lookup = chisel3.util.Lookup + + val Mux1H = chisel3.util.Mux1H + val PriorityMux = chisel3.util.PriorityMux + val MuxLookup = chisel3.util.MuxLookup + val MuxCase = chisel3.util.MuxCase + + val OHToUInt = chisel3.util.OHToUInt + val PriorityEncoder = chisel3.util.PriorityEncoder + val UIntToOH = chisel3.util.UIntToOH + val PriorityEncoderOH = chisel3.util.PriorityEncoderOH + + val RegNext = chisel3.util.RegNext + val RegInit = chisel3.util.RegInit + val RegEnable = chisel3.util.RegEnable + val ShiftRegister = chisel3.util.ShiftRegister + + type ValidIO[+T <: Data] = chisel3.util.Valid[T] + val Valid = chisel3.util.Valid + val Pipe = chisel3.util.Pipe + type Pipe[T <: Data] = chisel3.util.Pipe[T] + +} diff --git a/src/main/scala/Chisel/Main.scala b/src/main/scala/chisel3/compatibility/Main.scala index a72debc3..a41599a3 100644 --- a/src/main/scala/Chisel/Main.scala +++ b/src/main/scala/chisel3/compatibility/Main.scala @@ -1,9 +1,11 @@ // See LICENSE for license details. -package Chisel +package chisel3.compatibility import java.io.File +import chisel3._ + @deprecated("chiselMain doesn't exist in Chisel3", "3.0") object chiselMain { def apply[T <: Module](args: Array[String], gen: () => T): Unit = Predef.assert(false, "No more chiselMain in Chisel3") diff --git a/src/main/scala/chisel3/compatibility/debug.scala b/src/main/scala/chisel3/compatibility/debug.scala new file mode 100644 index 00000000..d9f6e4b0 --- /dev/null +++ b/src/main/scala/chisel3/compatibility/debug.scala @@ -0,0 +1,10 @@ +// See LICENSE for license details. + +package chisel3.compatibility + +import chisel3.core._ + +@deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3") +object debug { // scalastyle:ignore object.name + def apply (arg: Data): Data = arg +} diff --git a/src/main/scala/Chisel/throwException.scala b/src/main/scala/chisel3/compatibility/throwException.scala index 702884aa..3e8b33e6 100644 --- a/src/main/scala/Chisel/throwException.scala +++ b/src/main/scala/chisel3/compatibility/throwException.scala @@ -1,6 +1,8 @@ // See LICENSE for license details. -package Chisel +package chisel3.compatibility + +import chisel3._ @deprecated("throwException doesn't exist in Chisel3", "3.0.0") @throws(classOf[Exception]) diff --git a/src/main/scala/Chisel/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala index 7ca3268a..f1908089 100644 --- a/src/main/scala/Chisel/internal/firrtl/Emitter.scala +++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala @@ -1,10 +1,10 @@ // See LICENSE for license details. -package Chisel.internal.firrtl -import Chisel._ -import Chisel.internal.sourceinfo.{NoSourceInfo, SourceLine} +package chisel3.internal.firrtl +import chisel3._ +import chisel3.internal.sourceinfo.{NoSourceInfo, SourceLine} -private[Chisel] object Emitter { +private[chisel3] object Emitter { def emit(circuit: Circuit): String = new Emitter(circuit).toString } @@ -24,14 +24,14 @@ private class Emitter(circuit: Circuit) { case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}" case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}" case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}" - case e: Stop => s"stop(${e.clk.fullName(ctx)}, UInt<1>(1), ${e.ret})" - case e: Printf => s"""printf(${e.clk.fullName(ctx)}, UInt<1>(1), "${e.format}"${e.ids.map(_.fullName(ctx)).fold(""){_ + ", " + _}})""" + case e: Stop => s"stop(${e.clock.fullName(ctx)}, UInt<1>(1), ${e.ret})" + case e: Printf => + val (fmt, args) = e.pable.unpack(ctx) + val printfArgs = Seq(e.clock.fullName(ctx), "UInt<1>(1)", + "\"" + printf.format(fmt) + "\"") ++ args + printfArgs mkString ("printf(", ", ", ")") case e: DefInvalid => s"${e.arg.fullName(ctx)} is invalid" - case e: DefInstance => { - val modName = moduleMap.get(e.id.name).get - s"inst ${e.name} of $modName" - } - + case e: DefInstance => s"inst ${e.name} of ${e.id.modName}" case w: WhenBegin => indent() s"when ${w.pred.fullName(ctx)} :" @@ -46,18 +46,19 @@ private class Emitter(circuit: Circuit) { } // Map of Module FIRRTL definition to FIRRTL name, if it has been emitted already. - private val defnMap = collection.mutable.HashMap[String, String]() - // Map of Component name to FIRRTL id. - private val moduleMap = collection.mutable.HashMap[String, String]() + private val defnMap = collection.mutable.HashMap[(String, String), Component]() + + /** Generates the FIRRTL module declaration. + */ + private def moduleDecl(m: Component): String = m.id match { + case _: BlackBox => newline + s"extmodule ${m.name} : " + case _: Module => newline + s"module ${m.name} : " + } - /** Generates the FIRRTL module definition with a specified name. + /** Generates the FIRRTL module definition. */ - private def moduleDefn(m: Component, name: String): String = { + private def moduleDefn(m: Component): String = { val body = new StringBuilder - m.id match { - case _: BlackBox => body ++= newline + s"extmodule $name : " - case _: Module => body ++= newline + s"module $name : " - } withIndent { for (p <- m.ports) body ++= newline + emitPort(p) @@ -82,21 +83,16 @@ private class Emitter(circuit: Circuit) { */ private def emit(m: Component): String = { // Generate the body. - val moduleName = m.id.getClass.getName.split('.').last - val defn = moduleDefn(m, moduleName) + val defn = moduleDefn(m) - defnMap get defn match { - case Some(deduplicatedName) => - moduleMap(m.name) = deduplicatedName + defnMap get (m.id.desiredName, defn) match { + case Some(duplicate) => + m.id setModName duplicate.name "" case None => - require(!(moduleMap contains m.name), - "emitting module with same name but different contents") - - moduleMap(m.name) = m.name - defnMap(defn) = m.name - - moduleDefn(m, m.name) + defnMap((m.id.desiredName, defn)) = m + m.id setModName m.name + moduleDecl(m) + defn } } diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala new file mode 100644 index 00000000..17ddd55a --- /dev/null +++ b/src/main/scala/chisel3/package.scala @@ -0,0 +1,197 @@ +// See LICENSE for license details. + +package object chisel3 { // scalastyle:ignore package.object.name + import scala.language.experimental.macros + + import internal.firrtl.Width + import internal.sourceinfo.{SourceInfo, SourceInfoTransform} + import util.BitPat + + import chisel3.core.{Binding, FlippedBinder} + import chisel3.util._ + import chisel3.internal.firrtl.Port + + type Direction = chisel3.core.Direction + val Input = chisel3.core.Input + val Output = chisel3.core.Output + val Flipped = chisel3.core.Flipped + + type Data = chisel3.core.Data + val Wire = chisel3.core.Wire + val Clock = chisel3.core.Clock + type Clock = chisel3.core.Clock + + type Aggregate = chisel3.core.Aggregate + val Vec = chisel3.core.Vec + type Vec[T <: Data] = chisel3.core.Vec[T] + type VecLike[T <: Data] = chisel3.core.VecLike[T] + type Bundle = chisel3.core.Bundle + + val assert = chisel3.core.assert + + type Element = chisel3.core.Element + type Bits = chisel3.core.Bits + val Bits = chisel3.core.Bits + type Num[T <: Data] = chisel3.core.Num[T] + type UInt = chisel3.core.UInt + val UInt = chisel3.core.UInt + type SInt = chisel3.core.SInt + val SInt = chisel3.core.SInt + type Bool = chisel3.core.Bool + val Bool = chisel3.core.Bool + val Mux = chisel3.core.Mux + + type BlackBox = chisel3.core.BlackBox + + val Mem = chisel3.core.Mem + type MemBase[T <: Data] = chisel3.core.MemBase[T] + type Mem[T <: Data] = chisel3.core.Mem[T] + val SeqMem = chisel3.core.SeqMem + type SeqMem[T <: Data] = chisel3.core.SeqMem[T] + + val Module = chisel3.core.Module + type Module = chisel3.core.Module + + val printf = chisel3.core.printf + + val Reg = chisel3.core.Reg + + val when = chisel3.core.when + type WhenContext = chisel3.core.WhenContext + + type Printable = chisel3.core.Printable + val Printable = chisel3.core.Printable + type Printables = chisel3.core.Printables + val Printables = chisel3.core.Printables + type PString = chisel3.core.PString + val PString = chisel3.core.PString + type FirrtlFormat = chisel3.core.FirrtlFormat + val FirrtlFormat = chisel3.core.FirrtlFormat + type Decimal = chisel3.core.Decimal + val Decimal = chisel3.core.Decimal + type Hexadecimal = chisel3.core.Hexadecimal + val Hexadecimal = chisel3.core.Hexadecimal + type Binary = chisel3.core.Binary + val Binary = chisel3.core.Binary + type Character = chisel3.core.Character + val Character = chisel3.core.Character + type Name = chisel3.core.Name + val Name = chisel3.core.Name + type FullName = chisel3.core.FullName + val FullName = chisel3.core.FullName + val Percent = chisel3.core.Percent + + /** Implicit for custom Printable string interpolator */ + implicit class PrintableHelper(val sc: StringContext) extends AnyVal { + /** Custom string interpolator for generating Printables: p"..." + * Will call .toString on any non-Printable arguments (mimicking s"...") + */ + def p(args: Any*): Printable = { + sc.checkLengths(args) // Enforce sc.parts.size == pargs.size + 1 + val pargs: Seq[Option[Printable]] = args map { + case p: Printable => Some(p) + case d: Data => Some(d.toPrintable) + case any => for { + v <- Option(any) // Handle null inputs + str = v.toString + if !str.isEmpty // Handle empty Strings + } yield PString(str) + } + val parts = sc.parts map StringContext.treatEscapes + // Zip sc.parts and pargs together ito flat Seq + // eg. Seq(sc.parts(0), pargs(0), sc.parts(1), pargs(1), ...) + val seq = for { // append None because sc.parts.size == pargs.size + 1 + (literal, arg) <- parts zip (pargs :+ None) + optPable <- Seq(Some(PString(literal)), arg) + pable <- optPable // Remove Option[_] + } yield pable + Printables(seq) + } + } + + implicit def string2Printable(str: String): Printable = PString(str) + + /** + * These implicit classes allow one to convert scala.Int|scala.BigInt to + * Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively. + * The versions .asUInt(width)|.asSInt(width) are also available to explicitly + * mark a width for the new literal. + * + * Also provides .asBool to scala.Boolean and .asUInt to String + * + * Note that, for stylistic reasons, one should avoid extracting immediately + * after this call using apply, ie. 0.asUInt(1)(0) due to potential for + * confusion (the 1 is a bit length and the 0 is a bit extraction position). + * Prefer storing the result and then extracting from it. + */ + implicit class fromIntToLiteral(val x: Int) extends AnyVal { + def U: UInt = UInt(BigInt(x), Width()) // scalastyle:ignore method.name + def S: SInt = SInt(BigInt(x), Width()) // scalastyle:ignore method.name + + def asUInt(): UInt = UInt(x, Width()) + def asSInt(): SInt = SInt(x, Width()) + def asUInt(width: Int): UInt = UInt(x, width) + def asSInt(width: Int): SInt = SInt(x, width) + } + + implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal { + def U: UInt = UInt(x, Width()) // scalastyle:ignore method.name + def S: SInt = SInt(x, Width()) // scalastyle:ignore method.name + + def asUInt(): UInt = UInt(x, Width()) + def asSInt(): SInt = SInt(x, Width()) + def asUInt(width: Int): UInt = UInt(x, width) + def asSInt(width: Int): SInt = SInt(x, width) + } + implicit class fromStringToLiteral(val x: String) extends AnyVal { + def U: UInt = UInt(x) // scalastyle:ignore method.name + } + implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal { + def B: Bool = Bool(x) // scalastyle:ignore method.name + } + + implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal { + final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg + final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg + final def =/= (that: BitPat): Bool = macro SourceInfoTransform.thatArg + + def do_=== (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that === x // scalastyle:ignore method.name + def do_!= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that != x // scalastyle:ignore method.name + def do_=/= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that =/= x // scalastyle:ignore method.name + } + + // Compatibility with existing code. + val INPUT = chisel3.core.Direction.Input + val OUTPUT = chisel3.core.Direction.Output + val NODIR = chisel3.core.Direction.Unspecified + type ChiselException = chisel3.internal.ChiselException + + class EnqIO[+T <: Data](gen: T) extends DecoupledIO(gen) { + def init(): Unit = { + this.noenq() + } + override def cloneType: this.type = EnqIO(gen).asInstanceOf[this.type] + } + class DeqIO[+T <: Data](gen: T) extends DecoupledIO(gen) { + val Data = chisel3.core.Data + Data.setFirrtlDirection(this, Data.getFirrtlDirection(this).flip) + Binding.bind(this, FlippedBinder, "Error: Cannot flip ") + def init(): Unit = { + this.nodeq() + } + override def cloneType: this.type = DeqIO(gen).asInstanceOf[this.type] + } + object EnqIO { + def apply[T<:Data](gen: T): EnqIO[T] = new EnqIO(gen) + } + object DeqIO { + def apply[T<:Data](gen: T): DeqIO[T] = new DeqIO(gen) + } + + // Debugger/Tester access to internal Chisel data structures and methods. + def getDataElements(a: Aggregate): Seq[Element] = { + a.allElements + } + def getModulePorts(m: Module): Seq[Port] = m.getPorts + def getFirrtlDirection(d: Data): Direction = chisel3.core.Data.getFirrtlDirection(d) +} diff --git a/src/main/scala/Chisel/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala index b8c1494a..bd7d4027 100644 --- a/src/main/scala/Chisel/testers/BasicTester.scala +++ b/src/main/scala/chisel3/testers/BasicTester.scala @@ -1,7 +1,7 @@ // See LICENSE for license details. -package Chisel.testers -import Chisel._ +package chisel3.testers +import chisel3._ import scala.language.experimental.macros @@ -9,10 +9,11 @@ import internal._ import internal.Builder.pushCommand import internal.firrtl._ import internal.sourceinfo.SourceInfo +//import chisel3.core.ExplicitCompileOptions.NotStrict -class BasicTester extends Module { +class BasicTester extends Module() { // The testbench has no IOs, rather it should communicate using printf, assert, and stop. - val io = new Bundle() + val io = IO(new Bundle()) def popCount(n: Long): Int = n.toBinaryString.count(_=='1') diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala index a56bb8b7..586fa780 100644 --- a/src/main/scala/Chisel/testers/TesterDriver.scala +++ b/src/main/scala/chisel3/testers/TesterDriver.scala @@ -1,7 +1,8 @@ // See LICENSE for license details. -package Chisel.testers -import Chisel._ +package chisel3.testers + +import chisel3._ import scala.io.Source import scala.sys.process._ import java.io._ diff --git a/src/main/scala/Chisel/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index 16ae9be5..89bb644a 100644 --- a/src/main/scala/Chisel/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -3,18 +3,27 @@ /** Arbiters in all shapes and sizes. */ -package Chisel +package chisel3.util -/** An I/O bundle for the Arbiter */ +import chisel3._ +// TODO: remove this once we have CompileOptions threaded through the macro system. +import chisel3.core.ExplicitCompileOptions.NotStrict + +/** IO bundle definition for an Arbiter, which takes some number of ready-valid inputs and outputs + * (selects) at most one. + * + * @param gen data type + * @param n number of inputs + */ class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle { - val in = Vec(n, Decoupled(gen)).flip + val in = Flipped(Vec(n, Decoupled(gen))) val out = Decoupled(gen) - val chosen = UInt(OUTPUT, log2Up(n)) + val chosen = Output(UInt.width(log2Up(n))) } -/** Arbiter Control determining which producer has access */ -private object ArbiterCtrl -{ +/** Arbiter Control determining which producer has access + */ +private object ArbiterCtrl { def apply(request: Seq[Bool]): Seq[Bool] = request.length match { case 0 => Seq() case 1 => Seq(Bool(true)) @@ -25,7 +34,7 @@ private object ArbiterCtrl abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool]) extends Module { def grant: Seq[Bool] def choice: UInt - val io = new ArbiterIO(gen, n) + val io = IO(new ArbiterIO(gen, n)) io.chosen := choice io.out.valid := io.in(io.chosen).valid @@ -79,27 +88,29 @@ class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T } /** Hardware module that is used to sequence n producers into 1 consumer. - Producers are chosen in round robin order. - - Example usage: - val arb = new RRArbiter(2, UInt()) - arb.io.in(0) <> producer0.io.out - arb.io.in(1) <> producer1.io.out - consumer.io.in <> arb.io.out + * Producers are chosen in round robin order. + * + * @example {{{ + * val arb = new RRArbiter(2, UInt()) + * arb.io.in(0) <> producer0.io.out + * arb.io.in(1) <> producer1.io.out + * consumer.io.in <> arb.io.out + * }}} */ class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1) /** Hardware module that is used to sequence n producers into 1 consumer. - Priority is given to lower producer - - Example usage: - val arb = Module(new Arbiter(2, UInt())) - arb.io.in(0) <> producer0.io.out - arb.io.in(1) <> producer1.io.out - consumer.io.in <> arb.io.out - */ + * Priority is given to lower producer. + * + * @example {{{ + * val arb = Module(new Arbiter(2, UInt())) + * arb.io.in(0) <> producer0.io.out + * arb.io.in(1) <> producer1.io.out + * consumer.io.in <> arb.io.out + * }}} + */ class Arbiter[T <: Data](gen: T, n: Int) extends Module { - val io = new ArbiterIO(gen, n) + val io = IO(new ArbiterIO(gen, n)) io.chosen := UInt(n-1) io.out.bits := io.in(n-1).bits diff --git a/src/main/scala/Chisel/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala index 96206f63..972010a6 100644 --- a/src/main/scala/Chisel/BitPat.scala +++ b/src/main/scala/chisel3/util/BitPat.scala @@ -1,10 +1,11 @@ // See LICENSE for license details. -package Chisel +package chisel3.util import scala.language.experimental.macros -import Chisel.internal.sourceinfo.{SourceInfo, SourceInfoTransform} +import chisel3._ +import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform} object BitPat { /** Parses a bit pattern string into (bits, mask, width). @@ -36,7 +37,7 @@ object BitPat { /** Creates a [[BitPat]] literal from a string. * * @param n the literal value as a string, in binary, prefixed with 'b' - * @note legal characters are '0', '1', and '?', as well as '_' as white + * @note legal characters are '0', '1', and '?', as well as '_' and white * space (which are ignored) */ def apply(n: String): BitPat = { @@ -67,14 +68,15 @@ object BitPat { */ def apply(x: UInt): BitPat = { require(x.isLit) - BitPat("b" + x.litValue.toString(2)) + val len = if (x.isWidthKnown) x.getWidth else 0 + apply("b" + x.litValue.toString(2).reverse.padTo(len, "0").reverse.mkString) } } // TODO: Break out of Core? (this doesn't involve FIRRTL generation) /** Bit patterns are literals with masks, used to represent values with don't * cares. Equality comparisons will ignore don't care bits (for example, - * BitPat(0b10?1) === UInt(0b1001) and UInt(0b1011)). + * BitPat(0b10?1) === 0b1001.asUInt and 0b1011.asUInt. */ sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) { def getWidth: Int = width @@ -82,7 +84,7 @@ sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) { def =/= (that: UInt): Bool = macro SourceInfoTransform.thatArg def != (that: UInt): Bool = macro SourceInfoTransform.thatArg - def do_=== (that: UInt)(implicit sourceInfo: SourceInfo): Bool = UInt(value) === (that & UInt(mask)) - def do_=/= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = !(this === that) - def do_!= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = this =/= that + def do_=== (that: UInt)(implicit sourceInfo: SourceInfo): Bool = value.asUInt === (that & mask.asUInt) // scalastyle:ignore method.name + def do_=/= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = !(this === that) // scalastyle:ignore method.name + def do_!= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = this =/= that // scalastyle:ignore method.name } diff --git a/src/main/scala/Chisel/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala index 239a295e..289d27b1 100644 --- a/src/main/scala/Chisel/util/Bitwise.scala +++ b/src/main/scala/chisel3/util/Bitwise.scala @@ -3,12 +3,24 @@ /** Miscellaneous circuit generators operating on bits. */ -package Chisel +package chisel3.util -object FillInterleaved -{ +import chisel3._ +import chisel3.core.SeqUtils + +object FillInterleaved { + /** Creates n repetitions of each bit of x in order. + * + * Output data-equivalent to in(size(in)-1) (n times) ## ... ## in(1) (n times) ## in(0) (n times) + * For example, FillInterleaved(2, "b1000") === UInt("b11 00 00 00") + */ def apply(n: Int, in: UInt): UInt = apply(n, in.toBools) - def apply(n: Int, in: Seq[Bool]): UInt = Vec(in.map(Fill(n, _))).toBits + + /** Creates n repetitions of each bit of x in order. + * + * Output data-equivalent to in(size(in)-1) (n times) ## ... ## in(1) (n times) ## in(0) (n times) + */ + def apply(n: Int, in: Seq[Bool]): UInt = Cat(in.map(Fill(n, _)).reverse) } /** Returns the number of bits set (i.e value is 1) in the input signal. @@ -19,35 +31,29 @@ object PopCount def apply(in: Bits): UInt = apply((0 until in.getWidth).map(in(_))) } -/** Fill fans out a UInt to multiple copies */ object Fill { - /** Fan out x n times */ + /** Create n repetitions of x using a tree fanout topology. + * + * Output data-equivalent to x ## x ## ... ## x (n repetitions). + */ def apply(n: Int, x: UInt): UInt = { n match { - case 0 => UInt(width=0) + case 0 => UInt.width(0) case 1 => x - case y if n > 1 => + case _ if x.isWidthKnown && x.getWidth == 1 => + Mux(x.toBool, UInt((BigInt(1) << n) - 1, n), UInt(0, n)) + case _ if n > 1 => val p2 = Array.ofDim[UInt](log2Up(n + 1)) p2(0) = x for (i <- 1 until p2.length) p2(i) = Cat(p2(i-1), p2(i-1)) - Cat((0 until log2Up(y + 1)).filter(i => (y & (1 << i)) != 0).map(p2(_))) + Cat((0 until log2Up(n + 1)).filter(i => (n & (1 << i)) != 0).map(p2(_))) case _ => throw new IllegalArgumentException(s"n (=$n) must be nonnegative integer.") } } - /** Fan out x n times */ - def apply(n: Int, x: Bool): UInt = - if (n > 1) { - UInt(0,n) - x - } else { - apply(n, x: UInt) - } } -/** Litte/big bit endian convertion: reverse the order of the bits in a UInt. -*/ -object Reverse -{ +object Reverse { private def doit(in: UInt, length: Int): UInt = { if (length == 1) { in @@ -67,5 +73,7 @@ object Reverse Cat(doit(in(half-1,0), half), doit(in(length-1,half), length-half)) } } + /** Returns the input in bit-reversed order. Useful for little/big-endian conversion. + */ def apply(in: UInt): UInt = doit(in, in.getWidth) } diff --git a/src/main/scala/chisel3/util/Cat.scala b/src/main/scala/chisel3/util/Cat.scala new file mode 100644 index 00000000..ba12a7d4 --- /dev/null +++ b/src/main/scala/chisel3/util/Cat.scala @@ -0,0 +1,20 @@ +// See LICENSE for license details. + +package chisel3.util + +import chisel3._ +import chisel3.core.SeqUtils + +object Cat { + /** Concatenates the argument data elements, in argument order, together. + */ + def apply[T <: Bits](a: T, r: T*): UInt = apply(a :: r.toList) + + /** Concatenates the data elements of the input sequence, in reverse sequence order, together. + * The first element of the sequence forms the most significant bits, while the last element + * in the sequence forms the least significant bits. + * + * Equivalent to r(0) ## r(1) ## ... ## r(n-1). + */ + def apply[T <: Bits](r: Seq[T]): UInt = SeqUtils.asUInt(r.reverse) +} diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala new file mode 100644 index 00000000..d478e10e --- /dev/null +++ b/src/main/scala/chisel3/util/CircuitMath.scala @@ -0,0 +1,38 @@ +// See LICENSE for license details. + +/** Circuit-land math operations. + */ + +package chisel3.util + +import chisel3._ + +object Log2 { + /** Returns the base-2 integer logarithm of the least-significant `width` bits of an UInt. + * + * @note The result is truncated, so e.g. Log2(UInt(13)) === UInt(3) + */ + def apply(x: Bits, width: Int): UInt = { + if (width < 2) { + UInt(0) + } else if (width == 2) { + x(1) + } else if (width <= divideAndConquerThreshold) { + Mux(x(width-1), UInt(width-1), apply(x, width-1)) + } else { + val mid = 1 << (log2Ceil(width) - 1) + val hi = x(width-1, mid) + val lo = x(mid-1, 0) + val useHi = hi.orR + Cat(useHi, Mux(useHi, Log2(hi, width - mid), Log2(lo, mid))) + } + } + + /** Returns the base-2 integer logarithm of an UInt. + * + * @note The result is truncated, so e.g. Log2(UInt(13)) === UInt(3) + */ + def apply(x: Bits): UInt = apply(x, x.getWidth) + + private def divideAndConquerThreshold = 4 +} diff --git a/src/main/scala/chisel3/util/Conditional.scala b/src/main/scala/chisel3/util/Conditional.scala new file mode 100644 index 00000000..5830e014 --- /dev/null +++ b/src/main/scala/chisel3/util/Conditional.scala @@ -0,0 +1,94 @@ +// See LICENSE for license details. + +/** Conditional blocks. + */ + +package chisel3.util + +import scala.language.reflectiveCalls +import scala.language.experimental.macros +import scala.reflect.runtime.universe._ +import scala.reflect.macros.blackbox._ + +import chisel3._ + +object unless { // scalastyle:ignore object.name + /** Does the same thing as [[when$ when]], but with the condition inverted. + */ + def apply(c: Bool)(block: => Unit) { + when (!c) { block } + } +} + +/** Implementation details for [[switch]]. See [[switch]] and [[chisel3.util.is is]] for the + * user-facing API. + */ +class SwitchContext[T <: Bits](cond: T) { + def is(v: Iterable[T])(block: => Unit) { + if (!v.isEmpty) { + when (v.map(_.asUInt === cond.asUInt).reduce(_||_)) { + block + } + } + } + def is(v: T)(block: => Unit) { is(Seq(v))(block) } + def is(v: T, vr: T*)(block: => Unit) { is(v :: vr.toList)(block) } +} + +/** Use to specify cases in a [[switch]] block, equivalent to a [[when$ when]] block comparing to + * the condition variable. + * + * @note illegal outside a [[switch]] block + * @note multiple conditions may fire simultaneously + * @note dummy implementation, a macro inside [[switch]] transforms this into the actual + * implementation + */ +object is { // scalastyle:ignore object.name + // TODO: Begin deprecation of non-type-parameterized is statements. + /** Executes `block` if the switch condition is equal to any of the values in `v`. + */ + def apply(v: Iterable[Bits])(block: => Unit) { + require(false, "The 'is' keyword may not be used outside of a switch.") + } + + /** Executes `block` if the switch condition is equal to `v`. + */ + def apply(v: Bits)(block: => Unit) { + require(false, "The 'is' keyword may not be used outside of a switch.") + } + + /** Executes `block` if the switch condition is equal to any of the values in the argument list. + */ + def apply(v: Bits, vr: Bits*)(block: => Unit) { + require(false, "The 'is' keyword may not be used outside of a switch.") + } +} + +/** Conditional logic to form a switch block. See [[is$ is]] for the case API. + * + * @example {{{ + * switch (myState) { + * is (state1) { + * // some logic here that runs when myState === state1 + * } + * is (state2) { + * // some logic here that runs when myState === state2 + * } + * } + * }}} + */ +object switch { // scalastyle:ignore object.name + def apply[T <: Bits](cond: T)(x: => Unit): Unit = macro impl + def impl(c: Context)(cond: c.Tree)(x: c.Tree): c.Tree = { import c.universe._ + val sc = c.universe.internal.reificationSupport.freshTermName("sc") + def extractIsStatement(tree: Tree): List[c.universe.Tree] = tree match { + // TODO: remove when Chisel compatibility package is removed + case q"Chisel.`package`.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )") + case q"chisel3.util.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )") + case b => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.") + } + val q"..$body" = x + val ises = body.flatMap(extractIsStatement(_)) + q"""{ val $sc = new SwitchContext($cond); ..$ises }""" + } +} diff --git a/src/main/scala/Chisel/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala index 872e830a..ba66d667 100644 --- a/src/main/scala/Chisel/util/Counter.scala +++ b/src/main/scala/chisel3/util/Counter.scala @@ -1,14 +1,19 @@ // See LICENSE for license details. -package Chisel +package chisel3.util + +import chisel3._ +//import chisel3.core.ExplicitCompileOptions.Strict /** A counter module + * * @param n number of counts before the counter resets (or one more than the * maximum output value of the counter), need not be a power of two */ class Counter(val n: Int) { require(n >= 0) val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt(0) + /** Increment the counter, returning whether the counter currently is at the * maximum and will wrap. The incremented value is registered and will be * visible on the next cycle. @@ -27,14 +32,27 @@ class Counter(val n: Int) { } } -/** Counter Object - * Example Usage: - * {{{ val countOn = Bool(true) // increment counter every clock cycle - * val myCounter = Counter(countOn, n) - * when ( myCounter.value === UInt(3) ) { ... } }}}*/ object Counter { + /** Instantiate a [[Counter! counter]] with the specified number of counts. + */ def apply(n: Int): Counter = new Counter(n) + + /** Instantiate a [[Counter! counter]] with the specified number of counts and a gate. + * + * @param cond condition that controls whether the counter increments this cycle + * @param n number of counts before the counter resets + * @return tuple of the counter value and whether the counter will wrap (the value is at + * maximum and the condition is true). + * + * @example {{{ + * val countOn = Bool(true) // increment counter every clock cycle + * val (counterValue, counterWrap) = Counter(countOn, 4) + * when (counterValue === UInt(3)) { + * ... + * } + * }}} + */ def apply(cond: Bool, n: Int): (UInt, Bool) = { val c = new Counter(n) var wrap: Bool = null diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala new file mode 100644 index 00000000..a0cbf4f7 --- /dev/null +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -0,0 +1,269 @@ +// See LICENSE for license details. + +/** Wrappers for ready-valid (Decoupled) interfaces and associated circuit generators using them. + */ + +package chisel3.util + +import chisel3._ +// TODO: remove this once we have CompileOptions threaded through the macro system. +import chisel3.core.ExplicitCompileOptions.NotStrict + +/** An I/O Bundle containing 'valid' and 'ready' signals that handshake + * the transfer of data stored in the 'bits' subfield. + * The base protocol implied by the directionality is that the consumer + * uses the flipped interface. Actual semantics of ready/valid are + * enforced via use of concrete subclasses. + */ +abstract class ReadyValidIO[+T <: Data](gen: T) extends Bundle +{ + val ready = Input(Bool()) + val valid = Output(Bool()) + val bits = Output(gen.chiselCloneType) +} + +object ReadyValidIO { + + implicit class AddMethodsToReadyValid[T<:Data](val target: ReadyValidIO[T]) extends AnyVal { + def fire(): Bool = target.ready && target.valid + + /** push dat onto the output bits of this interface to let the consumer know it has happened. + * @param dat the values to assign to bits. + * @return dat. + */ + def enq(dat: T): T = { + target.valid := Bool(true) + target.bits := dat + dat + } + + /** Indicate no enqueue occurs. Valid is set to false, and all bits are set to zero. + */ + def noenq(): Unit = { + target.valid := Bool(false) + // We want the type from the following, not any existing binding. + target.bits := target.bits.cloneType.fromBits(0.asUInt) + } + + /** Assert ready on this port and return the associated data bits. + * This is typically used when valid has been asserted by the producer side. + * @param b ignored + * @return the data for this device, + */ + def deq(): T = { + target.ready := Bool(true) + target.bits + } + + /** Indicate no dequeue occurs. Ready is set to false + */ + def nodeq(): Unit = { + target.ready := Bool(false) + } + } +} + +/** A concrete subclass of ReadyValidIO signaling that the user expects a + * "decoupled" interface: 'valid' indicates that the producer has + * put valid data in 'bits', and 'ready' indicates that the consumer is ready + * to accept the data this cycle. No requirements are placed on the signaling + * of ready or valid. + */ +class DecoupledIO[+T <: Data](gen: T) extends ReadyValidIO[T](gen) +{ + override def cloneType: this.type = new DecoupledIO(gen).asInstanceOf[this.type] +} + +/** This factory adds a decoupled handshaking protocol to a data bundle. */ +object Decoupled +{ + /** Wraps some Data with a DecoupledIO interface. */ + def apply[T <: Data](gen: T): DecoupledIO[T] = new DecoupledIO(gen) + + /** Downconverts an IrrevocableIO output to a DecoupledIO, dropping guarantees of irrevocability. + * + * @note unsafe (and will error) on the producer (input) side of an IrrevocableIO + */ + def apply[T <: Data](irr: IrrevocableIO[T]): DecoupledIO[T] = { + require(irr.bits.flatten forall (_.dir == OUTPUT), "Only safe to cast produced Irrevocable bits to Decoupled.") + val d = Wire(new DecoupledIO(irr.bits)) + d.bits := irr.bits + d.valid := irr.valid + irr.ready := d.ready + d + } +// override def cloneType: this.type = { +// DeqIO(gen).asInstanceOf[this.type] +// } +} + +/** A concrete subclass of ReadyValidIO that promises to not change + * the value of 'bits' after a cycle where 'valid' is high and 'ready' is low. + * Additionally, once 'valid' is raised it will never be lowered until after + * 'ready' has also been raised. + */ +class IrrevocableIO[+T <: Data](gen: T) extends ReadyValidIO[T](gen) +{ + override def cloneType: this.type = new IrrevocableIO(gen).asInstanceOf[this.type] +} + +/** Factory adds an irrevocable handshaking protocol to a data bundle. */ +object Irrevocable +{ + def apply[T <: Data](gen: T): IrrevocableIO[T] = new IrrevocableIO(gen) + + /** Upconverts a DecoupledIO input to an IrrevocableIO, allowing an IrrevocableIO to be used + * where a DecoupledIO is expected. + * + * @note unsafe (and will error) on the consumer (output) side of an DecoupledIO + */ + def apply[T <: Data](dec: DecoupledIO[T]): IrrevocableIO[T] = { + require(dec.bits.flatten forall (_.dir == INPUT), "Only safe to cast consumed Decoupled bits to Irrevocable.") + val i = Wire(new IrrevocableIO(dec.bits)) + dec.bits := i.bits + dec.valid := i.valid + i.ready := dec.ready + i + } +} + +object EnqIO { + def apply[T<:Data](gen: T): DecoupledIO[T] = Decoupled(gen) +} +object DeqIO { + def apply[T<:Data](gen: T): DecoupledIO[T] = Flipped(Decoupled(gen)) +} + +/** An I/O Bundle for Queues + * @param gen The type of data to queue + * @param entries The max number of entries in the queue */ +class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle +{ + /** I/O to enqueue data, is [[Chisel.DecoupledIO]] flipped */ + val enq = DeqIO(gen) + /** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/ + val deq = EnqIO(gen) + /** The current amount of data in the queue */ + val count = Output(UInt.width(log2Up(entries + 1))) +} + +/** A hardware module implementing a Queue + * @param gen The type of data to queue + * @param entries The max number of entries in the queue + * @param pipe True if a single entry queue can run at full throughput (like a pipeline). The ''ready'' signals are + * combinationally coupled. + * @param flow True if the inputs can be consumed on the same cycle (the inputs "flow" through the queue immediately). + * The ''valid'' signals are coupled. + * + * @example {{{ + * val q = new Queue(UInt(), 16) + * q.io.enq <> producer.io.out + * consumer.io.in <> q.io.deq + * }}} + */ +class Queue[T <: Data](gen: T, + val entries: Int, + pipe: Boolean = false, + flow: Boolean = false, + override_reset: Option[Bool] = None) +extends Module(override_reset=override_reset) { + def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, _reset: Bool) = + this(gen, entries, pipe, flow, Some(_reset)) + + val io = IO(new QueueIO(gen, entries)) + + val ram = Mem(entries, gen) + val enq_ptr = Counter(entries) + val deq_ptr = Counter(entries) + val maybe_full = Reg(init=Bool(false)) + + val ptr_match = enq_ptr.value === deq_ptr.value + val empty = ptr_match && !maybe_full + val full = ptr_match && maybe_full + val do_enq = Wire(init=io.enq.fire()) + val do_deq = Wire(init=io.deq.fire()) + + when (do_enq) { + ram(enq_ptr.value) := io.enq.bits + enq_ptr.inc() + } + when (do_deq) { + deq_ptr.inc() + } + when (do_enq != do_deq) { + maybe_full := do_enq + } + + io.deq.valid := !empty + io.enq.ready := !full + io.deq.bits := ram(deq_ptr.value) + + if (flow) { + when (io.enq.valid) { io.deq.valid := Bool(true) } + when (empty) { + io.deq.bits := io.enq.bits + do_deq := Bool(false) + when (io.deq.ready) { do_enq := Bool(false) } + } + } + + if (pipe) { + when (io.deq.ready) { io.enq.ready := Bool(true) } + } + + val ptr_diff = enq_ptr.value - deq_ptr.value + if (isPow2(entries)) { + io.count := Cat(maybe_full && ptr_match, ptr_diff) + } else { + io.count := Mux(ptr_match, + Mux(maybe_full, + UInt(entries), UInt(0)), + Mux(deq_ptr.value > enq_ptr.value, + UInt(entries) + ptr_diff, ptr_diff)) + } +} + +/** Factory for a generic hardware queue. + * + * @param enq input (enqueue) interface to the queue, also determines width of queue elements + * @param entries depth (number of elements) of the queue + * + * @returns output (dequeue) interface from the queue + * + * @example {{{ + * consumer.io.in <> Queue(producer.io.out, 16) + * }}} + */ +object Queue +{ + /** Create a queue and supply a DecoupledIO containing the product. */ + def apply[T <: Data]( + enq: ReadyValidIO[T], + entries: Int = 2, + pipe: Boolean = false, + flow: Boolean = false): DecoupledIO[T] = { + val q = Module(new Queue(enq.bits.cloneType, entries, pipe, flow)) + q.io.enq.valid := enq.valid // not using <> so that override is allowed + q.io.enq.bits := enq.bits + enq.ready := q.io.enq.ready + TransitName(q.io.deq, q) + } + + /** Create a queue and supply a IrrevocableIO containing the product. + * Casting from Decoupled is safe here because we know the Queue has + * Irrevocable semantics; we didn't want to change the return type of + * apply() for backwards compatibility reasons. + */ + def irrevocable[T <: Data]( + enq: ReadyValidIO[T], + entries: Int = 2, + pipe: Boolean = false, + flow: Boolean = false): IrrevocableIO[T] = { + val deq = apply(enq, entries, pipe, flow) + val irr = Wire(new IrrevocableIO(deq.bits)) + irr.bits := deq.bits + irr.valid := deq.valid + deq.ready := irr.ready + irr + } +} diff --git a/src/main/scala/chisel3/util/Enum.scala b/src/main/scala/chisel3/util/Enum.scala new file mode 100644 index 00000000..55b595ee --- /dev/null +++ b/src/main/scala/chisel3/util/Enum.scala @@ -0,0 +1,53 @@ +// See LICENSE for license details. + +/** Enum generators, allowing circuit constants to have more meaningful names. + */ + +package chisel3.util + +import chisel3._ + +object Enum { + /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */ + private def createValues[T <: Bits](nodeType: T, n: Int): Seq[T] = + (0 until n).map(x => nodeType.fromInt(x, log2Up(n))) + + /** Returns n unique values of the specified type. Can be used with unpacking to define enums. + * + * @example {{{ + * val state_on :: state_off :: Nil = Enum(UInt(), 2) + * val current_state = UInt() + * switch (current_state) { + * is (state_on) { + * ... + * } + * if (state_off) { + * ... + * } + * } + * }}} + * + */ + def apply[T <: Bits](nodeType: T, n: Int): List[T] = createValues(nodeType, n).toList + + /** Returns a map of the input symbols to unique values of the specified type. + * + * @example {{{ + * val states = Enum(UInt(), 'on, 'off) + * val current_state = UInt() + * switch (current_state) { + * is (states('on)) { + * ... + * } + * if (states('off)) { + * .. + * } + * } + * }}} + */ + def apply[T <: Bits](nodeType: T, l: Symbol *): Map[Symbol, T] = (l zip createValues(nodeType, l.length)).toMap + + /** Returns a map of the input symbols to unique values of the specified type. + */ + def apply[T <: Bits](nodeType: T, l: List[Symbol]): Map[Symbol, T] = (l zip createValues(nodeType, l.length)).toMap +} diff --git a/src/main/scala/Chisel/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala index 6a230022..4d816a19 100644 --- a/src/main/scala/Chisel/ImplicitConversions.scala +++ b/src/main/scala/chisel3/util/ImplicitConversions.scala @@ -1,6 +1,8 @@ // See LICENSE for license details. -package Chisel +package chisel3.util + +import chisel3._ object ImplicitConversions { implicit def intToUInt(x: Int): UInt = UInt(x) diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala new file mode 100644 index 00000000..fedbf194 --- /dev/null +++ b/src/main/scala/chisel3/util/LFSR.scala @@ -0,0 +1,26 @@ +// See LICENSE for license details. + +/** LFSRs in all shapes and sizes. + */ + +package chisel3.util + +import chisel3._ +//import chisel3.core.ExplicitCompileOptions.Strict + +// scalastyle:off magic.number +object LFSR16 { + /** Generates a 16-bit linear feedback shift register, returning the register contents. + * May be useful for generating a pseudorandom sequence. + * + * @param increment optional control to gate when the LFSR updates. + */ + def apply(increment: Bool = Bool(true)): UInt = { + val width = 16 + val lfsr = Reg(init=UInt(1, width)) + when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) } + lfsr + } +} +// scalastyle:on magic.number + diff --git a/src/main/scala/Chisel/util/Lookup.scala b/src/main/scala/chisel3/util/Lookup.scala index 54922fc4..9e909c0c 100644 --- a/src/main/scala/Chisel/util/Lookup.scala +++ b/src/main/scala/chisel3/util/Lookup.scala @@ -1,6 +1,8 @@ // See LICENSE for license details. -package Chisel +package chisel3.util + +import chisel3._ object ListLookup { def apply[T <: Data](addr: UInt, default: List[T], mapping: Array[(BitPat, List[T])]): List[T] = { diff --git a/src/main/scala/Chisel/util/Math.scala b/src/main/scala/chisel3/util/Math.scala index 5f8212d8..73665f0f 100644 --- a/src/main/scala/Chisel/util/Math.scala +++ b/src/main/scala/chisel3/util/Math.scala @@ -3,7 +3,9 @@ /** Scala-land math helper functions, like logs. */ -package Chisel +package chisel3.util + +import chisel3._ /** Compute the log2 rounded up with min value of 1 */ object log2Up { diff --git a/src/main/scala/Chisel/util/Mux.scala b/src/main/scala/chisel3/util/Mux.scala index 9d92321a..245de67e 100644 --- a/src/main/scala/Chisel/util/Mux.scala +++ b/src/main/scala/chisel3/util/Mux.scala @@ -3,13 +3,17 @@ /** Mux circuit generators. */ -package Chisel +package chisel3.util + +import chisel3._ +import chisel3.core.SeqUtils /** Builds a Mux tree out of the input signal vector using a one hot encoded - select signal. Returns the output of the Mux tree. + * select signal. Returns the output of the Mux tree. + * + * @note results undefined if multiple select signals are simultaneously high */ -object Mux1H -{ +object Mux1H { def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T = apply(sel zip in) def apply[T <: Data](in: Iterable[(Bool, T)]): T = SeqUtils.oneHotMux(in) @@ -19,39 +23,39 @@ object Mux1H } /** Builds a Mux tree under the assumption that multiple select signals - can be enabled. Priority is given to the first select signal. - - Returns the output of the Mux tree. + * can be enabled. Priority is given to the first select signal. + * + * Returns the output of the Mux tree. */ -object PriorityMux -{ +object PriorityMux { def apply[T <: Data](in: Seq[(Bool, T)]): T = SeqUtils.priorityMux(in) def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T = apply(sel zip in) def apply[T <: Data](sel: Bits, in: Seq[T]): T = apply((0 until in.size).map(sel(_)), in) } -/** MuxLookup creates a cascade of n Muxs to search for a key value */ +/** Creates a cascade of n Muxs to search for a key value. */ object MuxLookup { /** @param key a key to search for * @param default a default value if nothing is found * @param mapping a sequence to search of keys and values * @return the value found or the default if not */ - def apply[S <: UInt, T <: Bits] (key: S, default: T, mapping: Seq[(S, T)]): T = { + def apply[S <: UInt, T <: Data] (key: S, default: T, mapping: Seq[(S, T)]): T = { var res = default for ((k, v) <- mapping.reverse) res = Mux(k === key, v, res) res } - } -/** MuxCase returns the first value that is enabled in a map of values */ +/** Given an association of values to enable signals, returns the first value with an associated + * high enable signal. + */ object MuxCase { /** @param default the default value if none are enabled * @param mapping a set of data values with associated enables * @return the first value in mapping that is enabled */ - def apply[T <: Bits] (default: T, mapping: Seq[(Bool, T)]): T = { + def apply[T <: Data] (default: T, mapping: Seq[(Bool, T)]): T = { var res = default for ((t, v) <- mapping.reverse){ res = Mux(t, v, res) diff --git a/src/main/scala/Chisel/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala index 73f27403..53ba8c3d 100644 --- a/src/main/scala/Chisel/util/OneHot.scala +++ b/src/main/scala/chisel3/util/OneHot.scala @@ -3,13 +3,19 @@ /** Circuit generators for working with one-hot representations. */ -package Chisel +package chisel3.util -/** Converts from One Hot Encoding to a UInt indicating which bit is active - * This is the inverse of [[Chisel.UIntToOH UIntToOH]]*/ +import chisel3._ + +/** Returns the bit position of the sole high bit of the input bitvector. + * + * Inverse operation of [[UIntToOH]]. + * + * @note assumes exactly one high bit, results undefined otherwise + */ object OHToUInt { - def apply(in: Seq[Bool]): UInt = apply(Vec(in)) - def apply(in: Vec[Bool]): UInt = apply(in.toBits, in.size) + def apply(in: Seq[Bool]): UInt = apply(Cat(in.reverse), in.size) + def apply(in: Vec[Bool]): UInt = apply(in.asUInt, in.size) def apply(in: Bits): UInt = apply(in, in.getWidth) def apply(in: Bits, width: Int): UInt = { @@ -24,9 +30,9 @@ object OHToUInt { } } -/** @return the bit position of the trailing 1 in the input vector - * with the assumption that multiple bits of the input bit vector can be set - * @example {{{ data_out := PriorityEncoder(data_in) }}} +/** Returns the bit position of the least-significant high bit of the input bitvector. + * + * Multiple bits may be high in the input. */ object PriorityEncoder { def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt(_))) @@ -35,8 +41,7 @@ object PriorityEncoder { /** Returns the one hot encoding of the input UInt. */ -object UIntToOH -{ +object UIntToOH { def apply(in: UInt, width: Int = -1): UInt = if (width == -1) { UInt(1) << in @@ -45,11 +50,10 @@ object UIntToOH } } -/** Returns a bit vector in which only the least-significant 1 bit in - the input vector, if any, is set. +/** Returns a bit vector in which only the least-significant 1 bit in the input vector, if any, + * is set. */ -object PriorityEncoderOH -{ +object PriorityEncoderOH { private def encode(in: Seq[Bool]): UInt = { val outs = Seq.tabulate(in.size)(i => UInt(BigInt(1) << i, in.size)) PriorityMux(in :+ Bool(true), outs :+ UInt(0, in.size)) diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala new file mode 100644 index 00000000..713a3b2e --- /dev/null +++ b/src/main/scala/chisel3/util/Reg.scala @@ -0,0 +1,66 @@ +// See LICENSE for license details. + +package chisel3.util + +import chisel3._ +// TODO: remove this once we have CompileOptions threaded through the macro system. +import chisel3.core.ExplicitCompileOptions.NotStrict + +object RegNext { + /** Returns a register with the specified next and no reset initialization. + * + * Essentially a 1-cycle delayed version of the input signal. + */ + def apply[T <: Data](next: T): T = Reg[T](null.asInstanceOf[T], next, null.asInstanceOf[T]) + + /** Returns a register with the specified next and reset initialization. + * + * Essentially a 1-cycle delayed version of the input signal. + */ + def apply[T <: Data](next: T, init: T): T = Reg[T](null.asInstanceOf[T], next, init) +} + +object RegInit { + /** Returns a register pre-initialized (on reset) to the specified value. + */ + def apply[T <: Data](init: T): T = Reg[T](null.asInstanceOf[T], null.asInstanceOf[T], init) +} + +object RegEnable { + /** Returns a register with the specified next, update enable gate, and no reset initialization. + */ + def apply[T <: Data](updateData: T, enable: Bool): T = { + val clonedUpdateData = updateData.chiselCloneType + val r = Reg(clonedUpdateData) + when (enable) { r := updateData } + r + } + + /** Returns a register with the specified next, update enable gate, and reset initialization. + */ + def apply[T <: Data](updateData: T, resetData: T, enable: Bool): T = { + val r = RegInit(resetData) + when (enable) { r := updateData } + r + } +} + +object ShiftRegister +{ + /** Returns the n-cycle delayed version of the input signal. + * + * @param in input to delay + * @param n number of cycles to delay + * @param en enable the shift + */ + def apply[T <: Data](in: T, n: Int, en: Bool = Bool(true)): T = { + // The order of tests reflects the expected use cases. + if (n == 1) { + RegEnable(in, en) + } else if (n != 0) { + RegNext(apply(in, n-1, en)) + } else { + in + } + } +} diff --git a/src/main/scala/chisel3/util/TransitName.scala b/src/main/scala/chisel3/util/TransitName.scala new file mode 100644 index 00000000..a3220a13 --- /dev/null +++ b/src/main/scala/chisel3/util/TransitName.scala @@ -0,0 +1,26 @@ +// See LICENSE for license details. + +package chisel3.util + +import chisel3._ +import internal.HasId + +/** + * The purpose of TransitName is to allow a library to 'move' a name + * call to a more appropriate place. + * For example, a library factory function may create a module and return + * the io. The only user-exposed field is that given IO, which can't use + * any name supplied by the user. This can add a hook so that the supplied + * name then names the Module. + * See Queue companion object for working example + */ +object TransitName { + def apply[T<:HasId](from: T, to: HasId): T = { + from.addPostnameHook((given_name: String) => {to.suggestName(given_name)}) + from + } + def withSuffix[T<:HasId](suffix: String)(from: T, to: HasId): T = { + from.addPostnameHook((given_name: String) => {to.suggestName(given_name + suffix)}) + from + } +} diff --git a/src/main/scala/Chisel/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala index 9e2202bb..3d153a2a 100644 --- a/src/main/scala/Chisel/util/Valid.scala +++ b/src/main/scala/chisel3/util/Valid.scala @@ -3,22 +3,24 @@ /** Wrappers for valid interfaces and associated circuit generators using them. */ -package Chisel +package chisel3.util -/** An I/O Bundle containing data and a signal determining if it is valid */ -class ValidIO[+T <: Data](gen2: T) extends Bundle +import chisel3._ +// TODO: remove this once we have CompileOptions threaded through the macro system. +import chisel3.core.ExplicitCompileOptions.NotStrict + +/** An Bundle containing data and a signal determining if it is valid */ +class Valid[+T <: Data](gen: T) extends Bundle { - val valid = Bool(OUTPUT) - val bits = gen2.cloneType.asOutput + val valid = Output(Bool()) + val bits = Output(gen.chiselCloneType) def fire(dummy: Int = 0): Bool = valid - override def cloneType: this.type = new ValidIO(gen2).asInstanceOf[this.type] + override def cloneType: this.type = Valid(gen).asInstanceOf[this.type] } -/** Adds a valid protocol to any interface. The standard used is - that the consumer uses the flipped interface. -*/ +/** Adds a valid protocol to any interface */ object Valid { - def apply[T <: Data](gen: T): ValidIO[T] = new ValidIO(gen) + def apply[T <: Data](gen: T): Valid[T] = new Valid(gen) } /** A hardware module that delays data coming down the pipeline @@ -32,7 +34,7 @@ object Valid { */ object Pipe { - def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): ValidIO[T] = { + def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): Valid[T] = { if (latency == 0) { val out = Wire(Valid(enqBits)) out.valid <> enqValid @@ -44,16 +46,16 @@ object Pipe apply(v, b, latency-1) } } - def apply[T <: Data](enqValid: Bool, enqBits: T): ValidIO[T] = apply(enqValid, enqBits, 1) - def apply[T <: Data](enq: ValidIO[T], latency: Int = 1): ValidIO[T] = apply(enq.valid, enq.bits, latency) + def apply[T <: Data](enqValid: Bool, enqBits: T): Valid[T] = apply(enqValid, enqBits, 1) + def apply[T <: Data](enq: Valid[T], latency: Int = 1): Valid[T] = apply(enq.valid, enq.bits, latency) } class Pipe[T <: Data](gen: T, latency: Int = 1) extends Module { - val io = new Bundle { - val enq = Valid(gen).flip - val deq = Valid(gen) - } + val io = IO(new Bundle { + val enq = Input(Valid(gen)) + val deq = Output(Valid(gen)) + }) io.deq <> Pipe(io.enq, latency) } diff --git a/src/main/scala/chisel3/util/util.scala b/src/main/scala/chisel3/util/util.scala new file mode 100644 index 00000000..812af21c --- /dev/null +++ b/src/main/scala/chisel3/util/util.scala @@ -0,0 +1,12 @@ +// See LICENSE for license details. + +package chisel3 + +package object util { + + /** Synonyms, moved from main package object - maintain scope. */ + type ValidIO[+T <: Data] = chisel3.util.Valid[T] + val ValidIO = chisel3.util.Valid + val DecoupledIO = chisel3.util.Decoupled + +} diff --git a/src/test/scala/chiselTests/AnnotatingExample.scala b/src/test/scala/chiselTests/AnnotatingExample.scala new file mode 100644 index 00000000..c84edf86 --- /dev/null +++ b/src/test/scala/chiselTests/AnnotatingExample.scala @@ -0,0 +1,145 @@ +// See LICENSE for license details. + +package chiselTests + +import chisel3._ +import chisel3.core.Module +import chisel3.internal.InstanceId +import chisel3.testers.BasicTester +import org.scalatest._ + +import scala.util.DynamicVariable + +//scalastyle:off magic.number + +/** + * This Spec file illustrates use of Donggyu's component name API, it currently only + * uses three methods .signalName, .parentModName and .pathName + * + * This is also an illustration of how to implement an annotation system in chisel3 + * A local (my) Driver and Builder are created to provide thread-local access to + * an annotation map, and then a post elaboration annotation processor can resolve + * the keys and could serialize the annotations to a file for use by firrtl passes + */ + +class SomeSubMod(param1: Int, param2: Int) extends Module { + val io = new Bundle { + val in = UInt(INPUT, 16) + val out = SInt(OUTPUT, 32) + } + val annotate = MyBuilder.myDynamicContext.annotationMap + + annotate(AnnotationKey(this, JustThisRef)) = s"SomeSubMod($param1, $param2)" + annotate(AnnotationKey(io.in, AllRefs)) = "sub mod io.in" + annotate(AnnotationKey(io.out, JustThisRef)) = "sub mod io.out" +} + +class AnnotatingExample extends Module { + val io = new Bundle { + val a = UInt(INPUT, 32) + val b = UInt(INPUT, 32) + val e = Bool(INPUT) + val z = UInt(OUTPUT, 32) + val v = Bool(OUTPUT) + val bun = new Bundle { + val nested_1 = UInt(INPUT, 12) + val nested_2 = Bool(OUTPUT) + } + } + val x = Reg(UInt(width = 32)) + val y = Reg(UInt(width = 32)) + + val subModule1 = Module(new SomeSubMod(1, 2)) + val subModule2 = Module(new SomeSubMod(3, 4)) + + + val annotate = MyBuilder.myDynamicContext.annotationMap + + annotate(AnnotationKey(subModule2, AllRefs)) = s"SomeSubMod was used" + + annotate(AnnotationKey(x, JustThisRef)) = "I am register X" + annotate(AnnotationKey(y, AllRefs)) = "I am register Y" + annotate(AnnotationKey(io.a, JustThisRef)) = "I am io.a" + annotate(AnnotationKey(io.bun.nested_1, AllRefs)) = "I am io.bun.nested_1" + annotate(AnnotationKey(io.bun.nested_2, JustThisRef)) = "I am io.bun.nested_2" +} + +class AnnotatingExampleTester extends BasicTester { + val dut = Module(new AnnotatingExample) + + stop() +} + +class AnnotatingExampleSpec extends FlatSpec with Matchers { + behavior of "Annotating components of a circuit" + + it should "contain the following relative keys" in { + val annotationMap = MyDriver.buildAnnotatedCircuit { () => new AnnotatingExampleTester } + + annotationMap.contains("SomeSubMod.io.in") should be(true) + annotationMap.contains("AnnotatingExample.y") should be(true) + + annotationMap("SomeSubMod.io.in") should be("sub mod io.in") + } + it should "contain the following absolute keys" in { + val annotationMap = MyDriver.buildAnnotatedCircuit { () => new AnnotatingExampleTester } + + annotationMap.contains("AnnotatingExampleTester.dut.subModule2.io.out") should be (true) + annotationMap.contains("AnnotatingExampleTester.dut.x") should be (true) + + annotationMap("AnnotatingExampleTester.dut.subModule2.io.out") should be ("sub mod io.out") + } +} + +trait AnnotationScope +case object AllRefs extends AnnotationScope +case object JustThisRef extends AnnotationScope + +object AnnotationKey { + def apply(component: InstanceId): AnnotationKey = { + AnnotationKey(component, AllRefs) + } +} +case class AnnotationKey(val component: InstanceId, scope: AnnotationScope) { + override def toString: String = { + scope match { + case JustThisRef => + s"${component.pathName}" + case AllRefs => + s"${component.parentModName}.${component.instanceName}" + case _ => + s"${component.toString}_unknown_scope" + } + } +} + +class AnnotationMap extends scala.collection.mutable.HashMap[AnnotationKey, String] + +class MyDynamicContext { + val annotationMap = new AnnotationMap +} + +object MyBuilder { + private val myDynamicContextVar = new DynamicVariable[Option[MyDynamicContext]](None) + + def myDynamicContext: MyDynamicContext = + myDynamicContextVar.value getOrElse new MyDynamicContext + + def processAnnotations(annotationMap: AnnotationMap): Map[String, String] = { + annotationMap.map { case (k,v) => k.toString -> v}.toMap + } + + def build[T <: Module](f: => T): Map[String, String] = { + myDynamicContextVar.withValue(Some(new MyDynamicContext)) { + Driver.emit(() => f) + processAnnotations(myDynamicContextVar.value.get.annotationMap) + } + } +} + +object MyDriver extends BackendCompilationUtilities { + /** + * illustrates a chisel3 style driver that, annotations can only processed within this structure + */ + def buildAnnotatedCircuit[T <: Module](gen: () => T): Map[String, String] = MyBuilder.build(Module(gen())) +}
\ No newline at end of file diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala index 24eb8b55..efc2e1e7 100644 --- a/src/test/scala/chiselTests/Assert.scala +++ b/src/test/scala/chiselTests/Assert.scala @@ -3,8 +3,9 @@ package chiselTests import org.scalatest._ -import Chisel._ -import Chisel.testers.BasicTester +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ class FailingAssertTester() extends BasicTester { assert(Bool(false)) @@ -25,7 +26,7 @@ class SucceedingAssertTester() extends BasicTester { } class PipelinedResetModule extends Module { - val io = new Bundle { } + val io = IO(new Bundle { }) val a = Reg(init = UInt(0xbeef)) val b = Reg(init = UInt(0xbeef)) assert(a === b) diff --git a/src/test/scala/chiselTests/BetterNamingTests.scala b/src/test/scala/chiselTests/BetterNamingTests.scala new file mode 100644 index 00000000..f5872adb --- /dev/null +++ b/src/test/scala/chiselTests/BetterNamingTests.scala @@ -0,0 +1,101 @@ +package chiselTests + +import org.scalatest.{FlatSpec, Matchers} +import collection.mutable + +import chisel3._ +import chisel3.util._ + +// Defined outside of the class so we don't get $ in name +class Other(w: Int) extends Module { + val io = new Bundle { + val a = UInt(width = w) + } +} +class PerNameIndexing(count: Int) extends Module { + val io = new Bundle { } + + val wires = Seq.tabulate(count) { i => Module(new Other(i)) } + val queues = Seq.tabulate(count) { i => Module(new Queue(UInt(width = i), 16)) } +} + +// Note this only checks Iterable[Chisel.Data] which excludes Maps +class IterableNaming extends Module { + val io = new Bundle { } + + val seq = Seq.tabulate(3) { i => + Seq.tabulate(2) { j => Wire(init = (i * j).U) } + } + val optSet = Some(Set(Wire(init = 0.U), + Wire(init = 1.U), + Wire(init = 2.U), + Wire(init = 3.U))) + + val stack = mutable.Stack[Module]() + for (i <- 0 until 4) { + stack push Module(new Other(i)) + } + + def streamFrom(x: Int): Stream[Module] = + Module(new Other(x)) #:: streamFrom(x + 1) + val stream = streamFrom(0) // Check that we don't get into infinite loop + val list = stream.take(8).toList +} + +/* Better Naming Tests + * + * These tests are intended to validate that Chisel picks better names + */ +class BetterNamingTests extends FlatSpec { + + behavior of "Better Naming" + + it should "provide unique counters for each name" in { + val verilog = Driver.emit(() => new PerNameIndexing(4)) + val ModuleDef = """\s*module\s+(\S+)\s+:\s*""".r + val expectedModules = Set("PerNameIndexing", + "Queue", "Queue_1", "Queue_2", "Queue_3", + "Other", "Other_1", "Other_2", "Other_3") + val foundModules = for { + ModuleDef(name) <- verilog.split("\n").toSeq + } yield name + assert(foundModules.toSet === expectedModules) + } + + it should "provide names for things defined in Iterable[HasId] and Option[HasId]" in { + val verilog = Driver.emit(() => new IterableNaming) + + val lines = verilog.split("\n").toSeq + + val SeqDef = """\s*wire\s+seq_(\d+)_(\d+)\s+:\s+UInt\s*""".r + val seqs = for { + i <- (0 until 3) + j <- (0 until 2) + } yield (i.toString, j.toString) + val foundSeqs = for { + SeqDef(i, j) <- lines + } yield (i, j) + assert(foundSeqs.toSet === seqs.toSet) + + val OptSetDef = """\s*wire\s+optSet_(\d+)\s+:\s+UInt\s*""".r + val optSets = (0 until 4) map (_.toString) + val foundOptSets = for { + OptSetDef(i) <- lines + } yield i + assert(foundOptSets.toSet === optSets.toSet) + + val StackDef = """\s*inst\s+stack_(\d+)\s+of\s+Other.*""".r + val stacks = (0 until 4) map (_.toString) + val foundStacks = for { + StackDef(i) <- lines + } yield i + assert(foundStacks.toSet === stacks.toSet) + + val ListDef = """\s*inst\s+list_(\d+)\s+of\s+Other.*""".r + val lists = (0 until 8) map (_.toString) + val foundLists = for { + ListDef(i) <- lines + } yield i + assert(foundLists.toSet === lists.toSet) + } +} diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala index 19aa956c..08999a1b 100644 --- a/src/test/scala/chiselTests/BitwiseOps.scala +++ b/src/test/scala/chiselTests/BitwiseOps.scala @@ -2,10 +2,10 @@ package chiselTests -import Chisel._ +import chisel3._ import org.scalatest._ import org.scalatest.prop._ -import Chisel.testers.BasicTester +import chisel3.testers.BasicTester class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester { val mask = (1 << w) - 1 diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala index ca94087c..344754e1 100644 --- a/src/test/scala/chiselTests/BlackBox.scala +++ b/src/test/scala/chiselTests/BlackBox.scala @@ -4,29 +4,32 @@ package chiselTests import java.io.File import org.scalatest._ -import Chisel._ -import Chisel.testers.BasicTester + +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ +//import chisel3.core.ExplicitCompileOptions.Strict class BlackBoxInverter extends BlackBox { - val io = new Bundle() { - val in = Bool(INPUT) - val out = Bool(OUTPUT) - } + val io = IO(new Bundle() { + val in = Input(Bool()) + val out = Output(Bool()) + }) } class BlackBoxPassthrough extends BlackBox { - val io = new Bundle() { - val in = Bool(INPUT) - val out = Bool(OUTPUT) - } + val io = IO(new Bundle() { + val in = Input(Bool()) + val out = Output(Bool()) + }) } class BlackBoxRegister extends BlackBox { - val io = new Bundle() { - val clock = Clock().asInput - val in = Bool(INPUT) - val out = Bool(OUTPUT) - } + val io = IO(new Bundle() { + val clock = Input(Clock()) + val in = Input(Bool()) + val out = Output(Bool()) + }) } class BlackBoxTester extends BasicTester { @@ -84,9 +87,9 @@ class BlackBoxWithClockTester extends BasicTester { /* // Must determine how to handle parameterized Verilog class BlackBoxConstant(value: Int) extends BlackBox { - val io = new Bundle() { - val out = UInt(width=log2Up(value)).asOutput - } + val io = IO(new Bundle() { + val out = Output(UInt(width=log2Up(value))) + }) override val name = s"#(WIDTH=${log2Up(value)},VALUE=$value) " } diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala index 658f5bb9..5b38ff6e 100644 --- a/src/test/scala/chiselTests/BundleWire.scala +++ b/src/test/scala/chiselTests/BundleWire.scala @@ -1,21 +1,22 @@ // See LICENSE for license details. package chiselTests -import Chisel._ +import chisel3._ import org.scalatest._ import org.scalatest.prop._ -import Chisel.testers.BasicTester +import chisel3.testers.BasicTester +//import chisel3.core.ExplicitCompileOptions.Strict class Coord extends Bundle { - val x = UInt(width = 32) - val y = UInt(width = 32) + val x = UInt.width( 32) + val y = UInt.width( 32) } class BundleWire(n: Int) extends Module { - val io = new Bundle { - val in = (new Coord).asInput - val outs = Vec(n, new Coord).asOutput - } + val io = IO(new Bundle { + val in = Input(new Coord) + val outs = Output(Vec(n, new Coord)) + }) val coords = Wire(Vec(n, new Coord)) for (i <- 0 until n) { coords(i) := io.in diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala index da68b0cb..d335bdf6 100644 --- a/src/test/scala/chiselTests/ChiselSpec.scala +++ b/src/test/scala/chiselTests/ChiselSpec.scala @@ -6,8 +6,8 @@ import java.io.File import org.scalatest._ import org.scalatest.prop._ import org.scalacheck._ -import Chisel._ -import Chisel.testers._ +import chisel3._ +import chisel3.testers._ /** Common utility functions for Chisel unit tests. */ trait ChiselRunners extends Assertions { diff --git a/src/test/scala/chiselTests/Clock.scala b/src/test/scala/chiselTests/Clock.scala new file mode 100644 index 00000000..79dd2de4 --- /dev/null +++ b/src/test/scala/chiselTests/Clock.scala @@ -0,0 +1,22 @@ +// See LICENSE for license details. + +package chiselTests + +import org.scalatest._ +import org.scalatest.prop._ + +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ + +class ClockAsUIntTester extends BasicTester { + assert(Bool(true).asClock.asUInt === UInt(1)) + stop() +} + + +class ClockSpec extends ChiselPropSpec { + property("Bool.asClock.asUInt should pass a signal through unaltered") { + assertTesterPasses { new ClockAsUIntTester } + } +} diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala new file mode 100644 index 00000000..57ceff3f --- /dev/null +++ b/src/test/scala/chiselTests/CompileOptionsTest.scala @@ -0,0 +1,285 @@ +// See LICENSE for license details. + +package chiselTests + +import org.scalatest._ +import chisel3._ +import chisel3.core.Binding.BindingException +import chisel3.core.ExplicitCompileOptions +import chisel3.testers.BasicTester +import chisel3.core.CompileOptions + +class CompileOptionsSpec extends ChiselFlatSpec { + + abstract class StrictModule extends Module()(chisel3.core.ExplicitCompileOptions.Strict) + abstract class NotStrictModule extends Module()(chisel3.core.ExplicitCompileOptions.NotStrict) + + // Generate a set of options that do not have requireIOWrap enabled, in order to + // ensure its definition comes from the implicit options passed to the Module constructor. + object StrictWithoutIOWrap extends CompileOptions { + val connectFieldsMustMatch = true + val declaredTypeMustBeUnbound = true + val requireIOWrap = false + val dontTryConnectionsSwapped = true + val dontAssumeDirectionality = true + val deprecateOldDirectionMethods = true + val checkSynthesizable = true + } + + class SmallBundle extends Bundle { + val f1 = UInt(width = 4) + val f2 = UInt(width = 5) + override def cloneType: this.type = (new SmallBundle).asInstanceOf[this.type] + } + class BigBundle extends SmallBundle { + val f3 = UInt(width = 6) + override def cloneType: this.type = (new BigBundle).asInstanceOf[this.type] + } + + "A Module with missing bundle fields when compiled with implicit Strict.CompileOption " should "throw an exception" in { + a [ChiselException] should be thrownBy { + import chisel3.core.ExplicitCompileOptions.Strict + + class ConnectFieldMismatchModule extends Module { + val io = IO(new Bundle { + val in = Input(new SmallBundle) + val out = Output(new BigBundle) + }) + io.out := io.in + } + elaborate { new ConnectFieldMismatchModule() } + } + } + + "A Module with missing bundle fields when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { + import chisel3.core.ExplicitCompileOptions.NotStrict + + class ConnectFieldMismatchModule extends Module { + val io = IO(new Bundle { + val in = Input(new SmallBundle) + val out = Output(new BigBundle) + }) + io.out := io.in + } + elaborate { new ConnectFieldMismatchModule() } + } + + "A Module in which a Reg is created with a bound type when compiled with implicit Strict.CompileOption " should "throw an exception" in { + a [BindingException] should be thrownBy { + import chisel3.core.ExplicitCompileOptions.Strict + + class CreateRegFromBoundTypeModule extends Module { + val io = IO(new Bundle { + val in = Input(new SmallBundle) + val out = Output(new BigBundle) + }) + val badReg = Reg(UInt(7, width=4)) + } + elaborate { new CreateRegFromBoundTypeModule() } + } + } + + "A Module in which a Reg is created with a bound type when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { + import chisel3.core.ExplicitCompileOptions.NotStrict + + class CreateRegFromBoundTypeModule extends Module { + val io = IO(new Bundle { + val in = Input(new SmallBundle) + val out = Output(new BigBundle) + }) + val badReg = Reg(UInt(7, width=4)) + } + elaborate { new CreateRegFromBoundTypeModule() } + } + + "A Module with wrapped IO when compiled with implicit Strict.CompileOption " should "not throw an exception" in { + import chisel3.core.ExplicitCompileOptions.Strict + + class RequireIOWrapModule extends Module { + val io = IO(new Bundle { + val in = UInt(width = 32).asInput + val out = Bool().asOutput + }) + io.out := io.in(1) + } + elaborate { new RequireIOWrapModule() } +} + + "A Module with unwrapped IO when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { + import chisel3.core.ExplicitCompileOptions.NotStrict + + class RequireIOWrapModule extends Module { + val io = new Bundle { + val in = UInt(width = 32).asInput + val out = Bool().asOutput + } + io.out := io.in(1) + } + elaborate { new RequireIOWrapModule() } + } + + "A Module with unwrapped IO when compiled with implicit Strict.CompileOption " should "throw an exception" in { + a [BindingException] should be thrownBy { + import chisel3.core.ExplicitCompileOptions.Strict + + class RequireIOWrapModule extends Module { + val io = new Bundle { + val in = UInt(width = 32).asInput + val out = Bool().asOutput + } + io.out := io.in(1) + } + elaborate { + new RequireIOWrapModule() + } + } + } + + "A Module connecting output as source to input as sink when compiled with implicit Strict.CompileOption " should "throw an exception" in { + a [ChiselException] should be thrownBy { + import chisel3.core.ExplicitCompileOptions.Strict + + class SimpleModule extends Module { + val io = IO(new Bundle { + val in = Input(UInt(width = 3)) + val out = Output(UInt(width = 4)) + }) + } + class SwappedConnectionModule extends SimpleModule { + val child = Module(new SimpleModule) + io.in := child.io.out + } + elaborate { new SwappedConnectionModule() } + } + } + + "A Module connecting output as source to input as sink when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { + import chisel3.core.ExplicitCompileOptions.NotStrict + + class SimpleModule extends Module { + val io = IO(new Bundle { + val in = Input(UInt(width = 3)) + val out = Output(UInt(width = 4)) + }) + } + class SwappedConnectionModule extends SimpleModule { + val child = Module(new SimpleModule) + io.in := child.io.out + } + elaborate { new SwappedConnectionModule() } + } + + "A Module with directionless connections when compiled with implicit Strict.CompileOption " should "throw an exception" in { + a [ChiselException] should be thrownBy { + // Verify we can suppress the inclusion of default compileOptions + import Chisel.{defaultCompileOptions => _, _} + import chisel3.core.ExplicitCompileOptions.Strict + + class SimpleModule extends Module { + val io = IO(new Bundle { + val in = Input(UInt(width = 3)) + val out = Output(UInt(width = 4)) + }) + val noDir = Wire(UInt(width = 3)) + } + + class DirectionLessConnectionModule extends SimpleModule { + val a = UInt(0, width = 3) + val b = Wire(UInt(width = 3)) + val child = Module(new SimpleModule) + b := child.noDir + } + elaborate { new DirectionLessConnectionModule() } + } + } + + "A Module with directionless connections when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { + import chisel3.core.ExplicitCompileOptions.NotStrict + + class SimpleModule extends Module { + val io = IO(new Bundle { + val in = Input(UInt(width = 3)) + val out = Output(UInt(width = 4)) + }) + val noDir = Wire(UInt(width = 3)) + } + + class DirectionLessConnectionModule extends SimpleModule { + val a = UInt(0, width = 3) + val b = Wire(UInt(width = 3)) + val child = Module(new SimpleModule) + b := child.noDir + } + elaborate { new DirectionLessConnectionModule() } + } + + "A Module with wrapped IO when compiled with explicit Strict.CompileOption " should "not throw an exception" in { + implicit val strictWithoutIOWrap = StrictWithoutIOWrap + class RequireIOWrapModule extends StrictModule { + val io = IO(new Bundle { + val in = UInt(width = 32).asInput + val out = Bool().asOutput + }) + io.out := io.in(1) + } + elaborate { + new RequireIOWrapModule() + } + } + + "A Module with unwrapped IO when compiled with explicit NotStrict.CompileOption " should "not throw an exception" in { + implicit val strictWithoutIOWrap = StrictWithoutIOWrap + class RequireIOWrapModule extends NotStrictModule { + val io = new Bundle { + val in = UInt(width = 32).asInput + val out = Bool().asOutput + } + io.out := io.in(1) + } + elaborate { + new RequireIOWrapModule() + } + } + + "A Module with unwrapped IO when compiled with explicit Strict.CompileOption " should "throw an exception" in { + a [BindingException] should be thrownBy { + implicit val strictWithoutIOWrap = StrictWithoutIOWrap + class RequireIOWrapModule extends StrictModule { + val io = new Bundle { + val in = UInt(width = 32).asInput + val out = Bool().asOutput + } + io.out := io.in(1) + } + elaborate { + new RequireIOWrapModule() + } + } + } + + "A Module with unwrapped IO when compiled with an explicit requireIOWrap false " should "not throw an exception" in { + + object StrictNotIOWrap { + + implicit object CompileOptions extends CompileOptions { + val connectFieldsMustMatch = true + val declaredTypeMustBeUnbound = true + val requireIOWrap = false + val dontTryConnectionsSwapped = true + val dontAssumeDirectionality = true + val deprecateOldDirectionMethods = false + val checkSynthesizable = true + } + + } + class NotIOWrapModule extends Module()(StrictNotIOWrap.CompileOptions) { + val io = new Bundle { + val in = UInt(width = 32).asInput + val out = Bool().asOutput + } + } + elaborate { + new NotIOWrapModule() + } + } +} diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala index d79a2625..0a1f31cc 100644 --- a/src/test/scala/chiselTests/ComplexAssign.scala +++ b/src/test/scala/chiselTests/ComplexAssign.scala @@ -1,25 +1,27 @@ // See LICENSE for license details. package chiselTests -import Chisel._ + import org.scalatest._ import org.scalatest.prop._ -import Chisel.testers.BasicTester +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ class Complex[T <: Data](val re: T, val im: T) extends Bundle { override def cloneType: this.type = - new Complex(re.cloneType, im.cloneType).asInstanceOf[this.type] + new Complex(re.chiselCloneType, im.chiselCloneType).asInstanceOf[this.type] } class ComplexAssign(w: Int) extends Module { - val io = new Bundle { - val e = new Bool(INPUT) - val in = new Complex(UInt(width = w), UInt(width = w)).asInput - val out = new Complex(UInt(width = w), UInt(width = w)).asOutput - } + val io = IO(new Bundle { + val e = Input(Bool()) + val in = Input(new Complex(UInt.width(w), UInt.width(w))) + val out = Output(new Complex(UInt.width(w), UInt.width(w))) + }) when (io.e) { - val tmp = Wire(new Complex(UInt(width = w), UInt(width = w))) + val tmp = Wire(new Complex(UInt.width(w), UInt.width(w))) tmp := io.in io.out.re := tmp.re io.out.im := tmp.im diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala index 07a76cdc..69d8a44a 100644 --- a/src/test/scala/chiselTests/Counter.scala +++ b/src/test/scala/chiselTests/Counter.scala @@ -1,10 +1,13 @@ // See LICENSE for license details. package chiselTests -import Chisel._ + import org.scalatest._ import org.scalatest.prop._ -import Chisel.testers.BasicTester + +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ class CountTester(max: Int) extends BasicTester { val cnt = Counter(max) diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala index e5cdfd07..b50a80c0 100644 --- a/src/test/scala/chiselTests/Decoder.scala +++ b/src/test/scala/chiselTests/Decoder.scala @@ -1,17 +1,20 @@ // See LICENSE for license details. package chiselTests -import Chisel._ + import org.scalatest._ import org.scalatest.prop._ import org.scalacheck._ -import Chisel.testers.BasicTester + +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ class Decoder(bitpats: List[String]) extends Module { - val io = new Bundle { - val inst = UInt(INPUT, 32) - val matched = Bool(OUTPUT) - } + val io = IO(new Bundle { + val inst = Input(UInt.width(32)) + val matched = Output(Bool()) + }) io.matched := Vec(bitpats.map(BitPat(_) === io.inst)).reduce(_||_) } diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala index 8f7937ab..d41c50e5 100644 --- a/src/test/scala/chiselTests/DeqIOSpec.scala +++ b/src/test/scala/chiselTests/DeqIOSpec.scala @@ -2,8 +2,9 @@ package chiselTests -import Chisel._ -import Chisel.testers.BasicTester +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ /** * Created by chick on 2/8/16. @@ -11,21 +12,21 @@ import Chisel.testers.BasicTester class UsesDeqIOInfo extends Bundle { val test_width = 32 - val info_data = UInt(width = test_width) + val info_data = UInt.width(test_width) } class UsesDeqIO extends Module { - val io = new Bundle { - val in = new DeqIO(new UsesDeqIOInfo) - val out = new EnqIO(new UsesDeqIOInfo) - } + val io = IO(new Bundle { + val in = chisel3.util.DeqIO(new UsesDeqIOInfo) + val out = chisel3.util.EnqIO(new UsesDeqIOInfo) + }) } class DeqIOSpec extends ChiselFlatSpec { runTester { new BasicTester { val dut = new UsesDeqIO - +/* "DeqIO" should "set the direction of it's parameter to INPUT" in { assert(dut.io.in.bits.info_data.dir === INPUT) } @@ -55,6 +56,7 @@ class DeqIOSpec extends ChiselFlatSpec { assert(dut.io.out.ready.dir == out_clone.ready.dir) assert(dut.io.out.valid.dir == out_clone.valid.dir) } + */ } } } diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala index dd2f6572..949b92ed 100644 --- a/src/test/scala/chiselTests/Direction.scala +++ b/src/test/scala/chiselTests/Direction.scala @@ -2,16 +2,16 @@ package chiselTests -import Chisel._ +import chisel3._ import org.scalatest._ import org.scalatest.prop._ -import Chisel.testers.BasicTester +import chisel3.testers.BasicTester class DirectionHaver extends Module { - val io = new Bundle { - val in = UInt(INPUT, 32) - val out = UInt(OUTPUT, 32) - } + val io = IO(new Bundle { + val in = Input(UInt.width(32)) + val out = Output(UInt.width(32)) + }) } class GoodDirection extends DirectionHaver { @@ -22,7 +22,7 @@ class BadDirection extends DirectionHaver { io.in := UInt(0) } -class DirectionSpec extends ChiselPropSpec { +class DirectionSpec extends ChiselPropSpec with ShouldMatchers { //TODO: In Chisel3 these are actually FIRRTL errors. Remove from tests? @@ -31,7 +31,8 @@ class DirectionSpec extends ChiselPropSpec { } property("Inputs should not be assignable") { - elaborate(new BadDirection) + a[Exception] should be thrownBy { + elaborate(new BadDirection) + } } - } diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala index 6600df2a..5f3e0dd1 100644 --- a/src/test/scala/chiselTests/EnableShiftRegister.scala +++ b/src/test/scala/chiselTests/EnableShiftRegister.scala @@ -1,15 +1,15 @@ // See LICENSE for license details. package chiselTests -import Chisel._ -import Chisel.testers.BasicTester +import chisel3._ +import chisel3.testers.BasicTester class EnableShiftRegister extends Module { - val io = new Bundle { - val in = UInt(INPUT, 4) - val shift = Bool(INPUT) - val out = UInt(OUTPUT, 4) - } + val io = IO(new Bundle { + val in = Input(UInt.width(4)) + val shift = Input(Bool()) + val out = Output(UInt.width(4)) + }) val r0 = Reg(init = UInt(0, 4)) val r1 = Reg(init = UInt(0, 4)) val r2 = Reg(init = UInt(0, 4)) diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala index a1bfffda..d683ce34 100644 --- a/src/test/scala/chiselTests/GCD.scala +++ b/src/test/scala/chiselTests/GCD.scala @@ -2,37 +2,37 @@ package chiselTests -import Chisel._ -import Chisel.testers.BasicTester +import chisel3._ +import chisel3.testers.BasicTester import org.scalatest._ import org.scalatest.prop._ class GCD extends Module { - val io = new Bundle { - val a = UInt(INPUT, 32) - val b = UInt(INPUT, 32) - val e = Bool(INPUT) - val z = UInt(OUTPUT, 32) - val v = Bool(OUTPUT) - } - val x = Reg(UInt(width = 32)) - val y = Reg(UInt(width = 32)) + val io = IO(new Bundle { + val a = Input(UInt.width(32)) + val b = Input(UInt.width(32)) + val e = Input(Bool()) + val z = Output(UInt.width(32)) + val v = Output(Bool()) + }) + val x = Reg(UInt.width( 32)) + val y = Reg(UInt.width( 32)) when (x > y) { x := x -% y } .otherwise { y := y -% x } when (io.e) { x := io.a; y := io.b } io.z := x - io.v := y === UInt(0) + io.v := y === 0.U } class GCDTester(a: Int, b: Int, z: Int) extends BasicTester { val dut = Module(new GCD) - val first = Reg(init=Bool(true)) - dut.io.a := UInt(a) - dut.io.b := UInt(b) + val first = Reg(init=true.B) + dut.io.a := a.U + dut.io.b := b.U dut.io.e := first when(first) { first := Bool(false) } - when(dut.io.v) { - assert(dut.io.z === UInt(z)) + when(!first && dut.io.v) { + assert(dut.io.z === z.U) stop() } } diff --git a/src/test/scala/chiselTests/Harness.scala b/src/test/scala/chiselTests/Harness.scala index bc838766..83f60391 100644 --- a/src/test/scala/chiselTests/Harness.scala +++ b/src/test/scala/chiselTests/Harness.scala @@ -1,13 +1,14 @@ // See LICENSE for license details. package chiselTests -import Chisel.testers.BasicTester + +import chisel3.testers.BasicTester import org.scalatest._ import org.scalatest.prop._ import java.io.File class HarnessSpec extends ChiselPropSpec - with Chisel.BackendCompilationUtilities { + with chisel3.BackendCompilationUtilities { def makeTrivialVerilog: (File => File) = makeHarness((prefix: String) => s""" module ${prefix}; diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala new file mode 100644 index 00000000..7bf3dded --- /dev/null +++ b/src/test/scala/chiselTests/IOCompatibility.scala @@ -0,0 +1,45 @@ +// See LICENSE for license details. + +package chiselTests + +import chisel3._ + +class IOCSimpleIO extends Bundle { + val in = Input(UInt(width=32)) + val out = Output(UInt(width=32)) +} + +class IOCPlusOne extends Module { + val io = IO(new IOCSimpleIO) + io.out := io.in + UInt(1) +} + +class IOCModuleVec(val n: Int) extends Module { + val io = IO(new Bundle { + val ins = Vec(n, Input(UInt(width=32))) + val outs = Vec(n, Output(UInt(width=32))) + }) + val pluses = Vec.fill(n){ Module(new IOCPlusOne).io } + for (i <- 0 until n) { + pluses(i).in := io.ins(i) + io.outs(i) := pluses(i).out + } +} + +class IOCModuleWire extends Module { + val io = IO(new IOCSimpleIO) + val inc = Wire(Module(new IOCPlusOne).io.chiselCloneType) + inc.in := io.in + io.out := inc.out +} + +class IOCompatibilitySpec extends ChiselPropSpec { + + property("IOCModuleVec should elaborate") { + elaborate { new IOCModuleVec(2) } + } + + property("IOCModuleWire should elaborate") { + elaborate { new IOCModuleWire } + } +} diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala index ed76a296..b13b67e3 100644 --- a/src/test/scala/chiselTests/LFSR16.scala +++ b/src/test/scala/chiselTests/LFSR16.scala @@ -1,14 +1,16 @@ // See LICENSE for license details. package chiselTests -import Chisel._ -import Chisel.testers.BasicTester + +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ class LFSR16 extends Module { - val io = new Bundle { - val inc = Bool(INPUT) - val out = UInt(OUTPUT, 16) - } + val io = IO(new Bundle { + val inc = Input(Bool()) + val out = Output(UInt.width(16)) + }) val res = Reg(init = UInt(1, 16)) when (io.inc) { val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1)) @@ -34,7 +36,7 @@ class LFSR16Tester(c: LFSR16) extends Tester(c) { } */ -//TODO: Use chisel.util version instead? +//TODO: Use chisel3.util version instead? class LFSRSpec extends ChiselPropSpec { diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala index 55b704a0..1d09f3c5 100644 --- a/src/test/scala/chiselTests/MemorySearch.scala +++ b/src/test/scala/chiselTests/MemorySearch.scala @@ -1,16 +1,17 @@ // See LICENSE for license details. package chiselTests -import Chisel._ -import Chisel.testers.BasicTester + +import chisel3._ +import chisel3.testers.BasicTester class MemorySearch extends Module { - val io = new Bundle { - val target = UInt(INPUT, 4) - val en = Bool(INPUT) - val done = Bool(OUTPUT) - val address = UInt(OUTPUT, 3) - } + val io = IO(new Bundle { + val target = Input(UInt.width(4)) + val en = Input(Bool()) + val done = Output(Bool()) + val address = Output(UInt.width(3)) + }) val vals = Array(0, 4, 15, 14, 2, 5, 13) val index = Reg(init = UInt(0, width = 3)) val elts = Vec(vals.map(UInt(_,4))) diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 88ba795b..7a4050db 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -1,23 +1,24 @@ // See LICENSE for license details. package chiselTests -import Chisel._ + +import chisel3._ class SimpleIO extends Bundle { - val in = UInt(INPUT, 32) - val out = UInt(OUTPUT, 32) + val in = Input(UInt.width(32)) + val out = Output(UInt.width(32)) } class PlusOne extends Module { - val io = new SimpleIO - io.out := io.in + UInt(1) + val io = IO(new SimpleIO) + io.out := io.in + 1.asUInt } class ModuleVec(val n: Int) extends Module { - val io = new Bundle { - val ins = Vec(n, UInt(INPUT, 32)) - val outs = Vec(n, UInt(OUTPUT, 32)) - } + val io = IO(new Bundle { + val ins = Input(Vec(n, UInt(32))) + val outs = Output(Vec(n, UInt(32))) + }) val pluses = Vec.fill(n){ Module(new PlusOne).io } for (i <- 0 until n) { pluses(i).in := io.ins(i) @@ -39,8 +40,8 @@ class ModuleVecTester(c: ModuleVec) extends Tester(c) { */ class ModuleWire extends Module { - val io = new SimpleIO - val inc = Wire(Module(new PlusOne).io) + val io = IO(new SimpleIO) + val inc = Wire(Module(new PlusOne).io.chiselCloneType) inc.in := io.in io.out := inc.out } @@ -57,10 +58,10 @@ class ModuleWireTester(c: ModuleWire) extends Tester(c) { */ class ModuleWhen extends Module { - val io = new Bundle { + val io = IO(new Bundle { val s = new SimpleIO val en = Bool() - } + }) when(io.en) { val inc = Module(new PlusOne).io inc.in := io.s.in diff --git a/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala b/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala new file mode 100644 index 00000000..f8206b9c --- /dev/null +++ b/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala @@ -0,0 +1,38 @@ +// See LICENSE for license details. + +package chiselTests + +class ModuleExplicitResetSpec extends ChiselFlatSpec { + + "A Module with an explicit reset in compatibility mode" should "elaborate" in { + import Chisel._ + val myReset = Bool(true) + class ModuleExplicitReset(reset: Bool) extends Module(_reset = reset) { + val io = new Bundle { + val done = Bool(OUTPUT) + } + + io.done := Bool(false) + } + + elaborate { + new ModuleExplicitReset(myReset) + } + } + + "A Module with an explicit reset in non-compatibility mode" should "elaborate" in { + import chisel3._ + val myReset = Bool(true) + class ModuleExplicitReset(reset: Bool) extends Module(_reset = reset) { + val io = IO(new Bundle { + val done = Bool(OUTPUT) + }) + + io.done := Bool(false) + } + + elaborate { + new ModuleExplicitReset(myReset) + } + } +} diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala index 49ba13c7..26ee4e03 100644 --- a/src/test/scala/chiselTests/MulLookup.scala +++ b/src/test/scala/chiselTests/MulLookup.scala @@ -2,17 +2,17 @@ package chiselTests -import Chisel._ +import chisel3._ import org.scalatest._ import org.scalatest.prop._ -import Chisel.testers.BasicTester +import chisel3.testers.BasicTester class MulLookup(val w: Int) extends Module { - val io = new Bundle { - val x = UInt(INPUT, w) - val y = UInt(INPUT, w) - val z = UInt(OUTPUT, 2 * w) - } + val io = IO(new Bundle { + val x = Input(UInt.width(w)) + val y = Input(UInt.width(w)) + val z = Output(UInt.width(2 * w)) + }) val tbl = Vec( for { i <- 0 until 1 << w diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala index 2f464123..fa4c4898 100644 --- a/src/test/scala/chiselTests/MultiAssign.scala +++ b/src/test/scala/chiselTests/MultiAssign.scala @@ -3,36 +3,43 @@ package chiselTests import org.scalatest._ -import Chisel._ -import Chisel.testers.BasicTester + +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ class LastAssignTester() extends BasicTester { val cnt = Counter(2) - val test = Wire(UInt(width=4)) - assert(test === UInt(7)) // allow read references before assign references + val test = Wire(UInt.width(4)) + assert(test === 7.U) // allow read references before assign references - test := UInt(13) - assert(test === UInt(7)) // output value should be position-independent + test := 13.U + assert(test === 7.U) // output value should be position-independent - test := UInt(7) - assert(test === UInt(7)) // this obviously should work + test := 7.U + assert(test === 7.U) // this obviously should work - when(cnt.value === UInt(1)) { + when(cnt.value === 1.U) { stop() } } class ReassignmentTester() extends BasicTester { - val test = UInt(15) - test := UInt(7) + val test = 15.U + test := 7.U } class MultiAssignSpec extends ChiselFlatSpec { "The last assignment" should "be used when multiple assignments happen" in { assertTesterPasses{ new LastAssignTester } } +} + +class IllegalAssignSpec extends ChiselFlatSpec { "Reassignments to non-wire types" should "be disallowed" in { - assertTesterFails{ new ReassignmentTester } + intercept[chisel3.internal.ChiselException] { + assertTesterFails{ new ReassignmentTester } + } } } diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala index c5a347e6..8e4c7579 100644 --- a/src/test/scala/chiselTests/OptionBundle.scala +++ b/src/test/scala/chiselTests/OptionBundle.scala @@ -3,20 +3,20 @@ package chiselTests import org.scalatest._ -import Chisel._ -import Chisel.testers.BasicTester +import chisel3._ +import chisel3.testers.BasicTester class OptionBundle(hasIn: Boolean) extends Bundle { val in = if (hasIn) { - Some(Bool(INPUT)) + Some(Input(Bool())) } else { None } - val out = Bool(OUTPUT) + val out = Output(Bool()) } class OptionBundleModule(hasIn: Boolean) extends Module { - val io = new OptionBundle(hasIn) + val io = IO(new OptionBundle(hasIn)) if (hasIn) { io.out := io.in.get } else { diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala index 999b7d36..42df6802 100644 --- a/src/test/scala/chiselTests/Padding.scala +++ b/src/test/scala/chiselTests/Padding.scala @@ -1,14 +1,15 @@ // See LICENSE for license details. package chiselTests -import Chisel._ + +import chisel3._ class Padder extends Module { - val io = new Bundle { - val a = Bits(INPUT, 4) - val asp = SInt(OUTPUT, 8) - val aup = UInt(OUTPUT, 8) - } + val io = IO(new Bundle { + val a = Input(UInt.width(4)) + val asp = Output(SInt.width(8)) + val aup = Output(UInt.width(8)) + }) io.asp := io.a.asSInt io.aup := io.a.asUInt } diff --git a/src/test/scala/chiselTests/ParameterizedModule.scala b/src/test/scala/chiselTests/ParameterizedModule.scala index 35e3ba78..14b21631 100644 --- a/src/test/scala/chiselTests/ParameterizedModule.scala +++ b/src/test/scala/chiselTests/ParameterizedModule.scala @@ -3,14 +3,14 @@ package chiselTests import org.scalatest._ -import Chisel._ -import Chisel.testers.BasicTester +import chisel3._ +import chisel3.testers.BasicTester class ParameterizedModule(invert: Boolean) extends Module { - val io = new Bundle { - val in = new Bool(INPUT) - val out = new Bool(OUTPUT) - } + val io = IO(new Bundle { + val in = Input(Bool()) + val out = Output(Bool()) + }) if (invert) { io.out := !io.in } else { diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala new file mode 100644 index 00000000..12564a40 --- /dev/null +++ b/src/test/scala/chiselTests/PrintableSpec.scala @@ -0,0 +1,187 @@ +package chiselTests + +import org.scalatest.{FlatSpec, Matchers} +import scala.collection.mutable + +import chisel3._ +import chisel3.testers.BasicTester + +/* Printable Tests */ +class PrintableSpec extends FlatSpec with Matchers { + private val PrintfRegex = """\s*printf\((.*)\).*""".r + // This regex is brittle, it relies on the first two arguments of the printf + // not containing quotes, problematic if Chisel were to emit UInt<1>("h01") + // instead of the current UInt<1>(1) for the enable signal + private val StringRegex = """([^"]*)"(.*?)"(.*)""".r + private case class Printf(str: String, args: Seq[String]) + private def getPrintfs(firrtl: String): Seq[Printf] = { + def processArgs(str: String): Seq[String] = + str split "," map (_.trim) filter (_.nonEmpty) + def processBody(str: String): (String, Seq[String]) = { + str match { + case StringRegex(_, fmt, args) => + (fmt, processArgs(args)) + case _ => fail(s"Regex to process Printf should work on $str!") + } + } + + firrtl split "\n" collect { + case PrintfRegex(matched) => + val (str, args) = processBody(matched) + Printf(str, args) + } + } + + behavior of "Printable & Custom Interpolator" + + it should "pass exact strings through" in { + class MyModule extends BasicTester { + printf(p"An exact string") + } + val firrtl = Driver.emit(() => new MyModule) + getPrintfs(firrtl) match { + case Seq(Printf("An exact string", Seq())) => + case e => fail() + } + } + it should "handle Printable and String concatination" in { + class MyModule extends BasicTester { + printf(p"First " + PString("Second ") + "Third") + } + val firrtl = Driver.emit(() => new MyModule) + getPrintfs(firrtl) match { + case Seq(Printf("First Second Third", Seq())) => + case e => fail() + } + } + it should "call toString on non-Printable objects" in { + class MyModule extends BasicTester { + val myInt = 1234 + printf(p"myInt = $myInt") + } + val firrtl = Driver.emit(() => new MyModule) + getPrintfs(firrtl) match { + case Seq(Printf("myInt = 1234", Seq())) => + case e => fail() + } + } + it should "generate proper printf for simple Decimal printing" in { + class MyModule extends BasicTester { + val myWire = Wire(init = UInt(1234)) + printf(p"myWire = ${Decimal(myWire)}") + } + val firrtl = Driver.emit(() => new MyModule) + getPrintfs(firrtl) match { + case Seq(Printf("myWire = %d", Seq("myWire"))) => + case e => fail() + } + } + it should "handle printing literals" in { + class MyModule extends BasicTester { + printf(Decimal(UInt(10, 32))) + } + val firrtl = Driver.emit(() => new MyModule) + getPrintfs(firrtl) match { + case Seq(Printf("%d", Seq(lit))) => + assert(lit contains "UInt<32>") + case e => fail() + } + } + it should "correctly escape percent" in { + class MyModule extends BasicTester { + printf(p"%") + } + val firrtl = Driver.emit(() => new MyModule) + getPrintfs(firrtl) match { + case Seq(Printf("%%", Seq())) => + case e => fail() + } + } + it should "support names of circuit elements including submodule IO" in { + // Submodule IO is a subtle issue because the Chisel element has a different + // parent module + class MySubModule extends Module { + val io = new Bundle { + val fizz = UInt(width = 32) + } + } + class MyBundle extends Bundle { + val foo = UInt(width = 32) + override def cloneType = (new MyBundle).asInstanceOf[this.type] + } + class MyModule extends BasicTester { + override def desiredName = "MyModule" + val myWire = Wire(new MyBundle) + val myInst = Module(new MySubModule) + printf(p"${Name(myWire.foo)}") + printf(p"${FullName(myWire.foo)}") + printf(p"${FullName(myInst.io.fizz)}") + } + val firrtl = Driver.emit(() => new MyModule) + println(firrtl) + getPrintfs(firrtl) match { + case Seq(Printf("foo", Seq()), + Printf("myWire.foo", Seq()), + Printf("myInst.io.fizz", Seq())) => + case e => fail() + } + } + it should "handle printing ports of submodules" in { + class MySubModule extends Module { + val io = new Bundle { + val fizz = UInt(width = 32) + } + } + class MyModule extends BasicTester { + val myInst = Module(new MySubModule) + printf(p"${myInst.io.fizz}") + } + val firrtl = Driver.emit(() => new MyModule) + getPrintfs(firrtl) match { + case Seq(Printf("%d", Seq("myInst.io.fizz"))) => + case e => fail() + } + } + it should "print UInts and SInts as Decimal by default" in { + class MyModule extends BasicTester { + val myUInt = Wire(init = UInt(0)) + val mySInt = Wire(init = SInt(-1)) + printf(p"$myUInt & $mySInt") + } + val firrtl = Driver.emit(() => new MyModule) + getPrintfs(firrtl) match { + case Seq(Printf("%d & %d", Seq("myUInt", "mySInt"))) => + case e => fail() + } + } + it should "print Vecs like Scala Seqs by default" in { + class MyModule extends BasicTester { + val myVec = Wire(Vec(4, UInt(width = 32))) + myVec foreach (_ := UInt(0)) + printf(p"$myVec") + } + val firrtl = Driver.emit(() => new MyModule) + getPrintfs(firrtl) match { + case Seq(Printf("Vec(%d, %d, %d, %d)", + Seq("myVec[0]", "myVec[1]", "myVec[2]", "myVec[3]"))) => + case e => fail() + } + } + it should "print Bundles like Scala Maps by default" in { + class MyModule extends BasicTester { + val myBun = Wire(new Bundle { + val foo = UInt(width = 32) + val bar = UInt(width = 32) + }) + myBun.foo := UInt(0) + myBun.bar := UInt(0) + printf(p"$myBun") + } + val firrtl = Driver.emit(() => new MyModule) + getPrintfs(firrtl) match { + case Seq(Printf("Bundle(foo -> %d, bar -> %d)", + Seq("myBun.foo", "myBun.bar"))) => + case e => fail() + } + } +} diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala index eb8b4b25..28b6132b 100644 --- a/src/test/scala/chiselTests/Printf.scala +++ b/src/test/scala/chiselTests/Printf.scala @@ -3,8 +3,9 @@ package chiselTests import org.scalatest._ -import Chisel._ -import Chisel.testers.BasicTester +import chisel3._ +import chisel3.util._ +import chisel3.testers.BasicTester class SinglePrintfTester() extends BasicTester { val x = UInt(254) @@ -24,6 +25,11 @@ class MultiPrintfTester() extends BasicTester { stop() } +class ASCIIPrintableTester extends BasicTester { + printf(PString((0x20 to 0x7e) map (_.toChar) mkString "")) + stop() +} + class PrintfSpec extends ChiselFlatSpec { "A printf with a single argument" should "run" in { assertTesterPasses { new SinglePrintfTester } @@ -34,4 +40,7 @@ class PrintfSpec extends ChiselFlatSpec { "A printf with ASCII characters 1-127" should "run" in { assertTesterPasses { new ASCIIPrintfTester } } + "A printf with Printable ASCII characters 1-127" should "run" in { + assertTesterPasses { new ASCIIPrintableTester } + } } diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala index f2620d88..a9086223 100644 --- a/src/test/scala/chiselTests/Reg.scala +++ b/src/test/scala/chiselTests/Reg.scala @@ -3,8 +3,9 @@ package chiselTests import org.scalatest._ -import Chisel._ -import Chisel.testers.BasicTester +import chisel3._ +import chisel3.core.DataMirror +import chisel3.testers.BasicTester class RegSpec extends ChiselFlatSpec { "A Reg" should "throw an exception if not given any parameters" in { @@ -15,20 +16,23 @@ class RegSpec extends ChiselFlatSpec { "A Reg" should "be of the same type and width as outType, if specified" in { class RegOutTypeWidthTester extends BasicTester { - val reg = Reg(t=UInt(width=2), next=UInt(width=3), init=UInt(20)) - reg.width.get should be (2) + val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt(20)) + reg.getWidth should be (2) } elaborate{ new RegOutTypeWidthTester } } "A Reg" should "be of unknown width if outType is not specified and width is not forced" in { class RegUnknownWidthTester extends BasicTester { - val reg1 = Reg(next=UInt(width=3), init=UInt(20)) - reg1.width.known should be (false) + val reg1 = Reg(next=Wire(UInt(width=3)), init=UInt(20)) + reg1.isWidthKnown should be (false) + DataMirror.widthOf(reg1).known should be (false) val reg2 = Reg(init=UInt(20)) - reg2.width.known should be (false) - val reg3 = Reg(next=UInt(width=3), init=UInt(width=5)) - reg3.width.known should be (false) + reg2.isWidthKnown should be (false) + DataMirror.widthOf(reg2).known should be (false) + val reg3 = Reg(next=Wire(UInt(width=3)), init=UInt(5)) + reg3.isWidthKnown should be (false) + DataMirror.widthOf(reg3).known should be (false) } elaborate { new RegUnknownWidthTester } } @@ -36,7 +40,7 @@ class RegSpec extends ChiselFlatSpec { "A Reg" should "be of width of init if outType and next are missing and init is a literal of forced width" in { class RegForcedWidthTester extends BasicTester { val reg2 = Reg(init=UInt(20, width=7)) - reg2.width.get should be (7) + reg2.getWidth should be (7) } elaborate{ new RegForcedWidthTester } } diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala index 3daa5bd2..6d5a0a76 100644 --- a/src/test/scala/chiselTests/Risc.scala +++ b/src/test/scala/chiselTests/Risc.scala @@ -1,23 +1,25 @@ // See LICENSE for license details. package chiselTests -import Chisel._ + +import chisel3._ +import chisel3.util._ class Risc extends Module { - val io = new Bundle { - val isWr = Bool(INPUT) - val wrAddr = UInt(INPUT, 8) - val wrData = Bits(INPUT, 32) - val boot = Bool(INPUT) - val valid = Bool(OUTPUT) - val out = Bits(OUTPUT, 32) - } + val io = IO(new Bundle { + val isWr = Input(Bool()) + val wrAddr = Input(UInt.width(8)) + val wrData = Input(Bits.width(32)) + val boot = Input(Bool()) + val valid = Output(Bool()) + val out = Output(Bits.width(32)) + }) val memSize = 256 - val file = Mem(memSize, Bits(width = 32)) - val code = Mem(memSize, Bits(width = 32)) + val file = Mem(memSize, Bits.width(32)) + val code = Mem(memSize, Bits.width(32)) val pc = Reg(init=UInt(0, 8)) - val add_op :: imm_op :: Nil = Enum(Bits(width = 8), 2) + val add_op :: imm_op :: Nil = Enum(Bits.width(8), 2) val inst = code(pc) val op = inst(31,24) @@ -25,13 +27,13 @@ class Risc extends Module { val rai = inst(15, 8) val rbi = inst( 7, 0) - val ra = Mux(rai === Bits(0), Bits(0), file(rai)) - val rb = Mux(rbi === Bits(0), Bits(0), file(rbi)) - val rc = Wire(Bits(width = 32)) + val ra = Mux(rai === 0.asUInt(), 0.asUInt(), file(rai)) + val rb = Mux(rbi === 0.asUInt(), 0.asUInt(), file(rbi)) + val rc = Wire(Bits.width(32)) io.valid := Bool(false) - io.out := Bits(0) - rc := Bits(0) + io.out := 0.asUInt() + rc := 0.asUInt() when (io.isWr) { code(io.wrAddr) := io.wrData @@ -43,12 +45,12 @@ class Risc extends Module { is(imm_op) { rc := (rai << 8) | rbi } } io.out := rc - when (rci === UInt(255)) { + when (rci === 255.asUInt()) { io.valid := Bool(true) } .otherwise { file(rci) := rc } - pc := pc +% UInt(1) + pc := pc +% 1.asUInt() } } diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala index 0835fb4d..392c4803 100644 --- a/src/test/scala/chiselTests/SIntOps.scala +++ b/src/test/scala/chiselTests/SIntOps.scala @@ -1,28 +1,29 @@ // See LICENSE for license details. package chiselTests -import Chisel._ -import Chisel.testers.BasicTester + +import chisel3._ +import chisel3.testers.BasicTester class SIntOps extends Module { - val io = new Bundle { - val a = SInt(INPUT, 16) - val b = SInt(INPUT, 16) - val addout = SInt(OUTPUT, 16) - val subout = SInt(OUTPUT, 16) - val timesout = SInt(OUTPUT, 16) - val divout = SInt(OUTPUT, 16) - val modout = SInt(OUTPUT, 16) - val lshiftout = SInt(OUTPUT, 16) - val rshiftout = SInt(OUTPUT, 16) - val lessout = Bool(OUTPUT) - val greatout = Bool(OUTPUT) - val eqout = Bool(OUTPUT) - val noteqout = Bool(OUTPUT) - val lesseqout = Bool(OUTPUT) - val greateqout = Bool(OUTPUT) - val negout = SInt(OUTPUT, 16) - } + val io = IO(new Bundle { + val a = Input(SInt.width(16)) + val b = Input(SInt.width(16)) + val addout = Output(SInt.width(16)) + val subout = Output(SInt.width(16)) + val timesout = Output(SInt.width(16)) + val divout = Output(SInt.width(16)) + val modout = Output(SInt.width(16)) + val lshiftout = Output(SInt.width(16)) + val rshiftout = Output(SInt.width(16)) + val lessout = Output(Bool()) + val greatout = Output(Bool()) + val eqout = Output(Bool()) + val noteqout = Output(Bool()) + val lesseqout = Output(Bool()) + val greateqout = Output(Bool()) + val negout = Output(SInt.width(16)) + }) val a = io.a val b = io.b diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index ac799c8a..a72af928 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -1,19 +1,22 @@ // See LICENSE for license details. package chiselTests + import scala.collection.mutable.Stack -import Chisel._ + +import chisel3._ +import chisel3.util._ class ChiselStack(val depth: Int) extends Module { - val io = new Bundle { - val push = Bool(INPUT) - val pop = Bool(INPUT) - val en = Bool(INPUT) - val dataIn = UInt(INPUT, 32) - val dataOut = UInt(OUTPUT, 32) - } + val io = IO(new Bundle { + val push = Input(Bool()) + val pop = Input(Bool()) + val en = Input(Bool()) + val dataIn = Input(UInt.width(32)) + val dataOut = Output(UInt.width(32)) + }) - val stack_mem = Mem(depth, UInt(width = 32)) + val stack_mem = Mem(depth, UInt.width(32)) val sp = Reg(init = UInt(0, width = log2Up(depth + 1))) val out = Reg(init = UInt(0, width = 32)) diff --git a/src/test/scala/chiselTests/Stop.scala b/src/test/scala/chiselTests/Stop.scala index 878f090c..4afb077a 100644 --- a/src/test/scala/chiselTests/Stop.scala +++ b/src/test/scala/chiselTests/Stop.scala @@ -3,8 +3,8 @@ package chiselTests import org.scalatest._ -import Chisel._ -import Chisel.testers.BasicTester +import chisel3._ +import chisel3.testers.BasicTester class StopTester() extends BasicTester { stop() diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index c79eb8a4..66a06435 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -2,20 +2,22 @@ package chiselTests -import Chisel._ import org.scalatest._ import org.scalatest.prop._ -import Chisel.testers.BasicTester + +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ class Tbl(w: Int, n: Int) extends Module { - val io = new Bundle { - val wi = UInt(INPUT, log2Up(n)) - val ri = UInt(INPUT, log2Up(n)) - val we = Bool(INPUT) - val d = UInt(INPUT, w) - val o = UInt(OUTPUT, w) - } - val m = Mem(n, UInt(width = w)) + val io = IO(new Bundle { + val wi = Input(UInt.width(log2Up(n))) + val ri = Input(UInt.width(log2Up(n))) + val we = Input(Bool()) + val d = Input(UInt.width(w)) + val o = Output(UInt.width(w)) + }) + val m = Mem(n, UInt.width(w)) io.o := m(io.ri) when (io.we) { m(io.wi) := io.d diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala index 3c57daae..b2e811d9 100644 --- a/src/test/scala/chiselTests/TesterDriverSpec.scala +++ b/src/test/scala/chiselTests/TesterDriverSpec.scala @@ -2,8 +2,10 @@ package chiselTests -import Chisel._ -import Chisel.testers.BasicTester +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ +//import chisel3.core.ExplicitCompileOptions.Strict /** Extend BasicTester with a simple circuit and finish method. TesterDriver will call the * finish method after the FinishTester's constructor has completed, which will alter the @@ -19,7 +21,7 @@ class FinishTester extends BasicTester { stop() } - val test_wire = Wire(UInt(1, width = test_wire_width)) + val test_wire = Wire(init=UInt(1, test_wire_width)) // though we just set test_wire to 1, the assert below will pass because // the finish will change its value diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala index bb0b0f06..ad5aecd8 100644 --- a/src/test/scala/chiselTests/UIntOps.scala +++ b/src/test/scala/chiselTests/UIntOps.scala @@ -1,28 +1,29 @@ // See LICENSE for license details. package chiselTests -import Chisel._ + +import chisel3._ import org.scalatest._ -import Chisel.testers.BasicTester +import chisel3.testers.BasicTester class UIntOps extends Module { - val io = new Bundle { - val a = UInt(INPUT, 16) - val b = UInt(INPUT, 16) - val addout = UInt(OUTPUT, 16) - val subout = UInt(OUTPUT, 16) - val timesout = UInt(OUTPUT, 16) - val divout = UInt(OUTPUT, 16) - val modout = UInt(OUTPUT, 16) - val lshiftout = UInt(OUTPUT, 16) - val rshiftout = UInt(OUTPUT, 16) - val lessout = Bool(OUTPUT) - val greatout = Bool(OUTPUT) - val eqout = Bool(OUTPUT) - val noteqout = Bool(OUTPUT) - val lesseqout = Bool(OUTPUT) - val greateqout = Bool(OUTPUT) - } + val io = IO(new Bundle { + val a = Input(UInt.width(16)) + val b = Input(UInt.width(16)) + val addout = Output(UInt.width(16)) + val subout = Output(UInt.width(16)) + val timesout = Output(UInt.width(16)) + val divout = Output(UInt.width(16)) + val modout = Output(UInt.width(16)) + val lshiftout = Output(UInt.width(16)) + val rshiftout = Output(UInt.width(16)) + val lessout = Output(Bool()) + val greatout = Output(Bool()) + val eqout = Output(Bool()) + val noteqout = Output(Bool()) + val lesseqout = Output(Bool()) + val greateqout = Output(Bool()) + }) val a = io.a val b = io.b @@ -76,18 +77,18 @@ class UIntOpsTester(c: UIntOps) extends Tester(c) { */ class GoodBoolConversion extends Module { - val io = new Bundle { - val u = UInt(1, width = 1).asInput - val b = Bool(OUTPUT) - } + val io = IO(new Bundle { + val u = Input(UInt.width(1)) + val b = Output(Bool()) + }) io.b := io.u.toBool } class BadBoolConversion extends Module { - val io = new Bundle { - val u = UInt(1, width = 5).asInput - val b = Bool(OUTPUT) - } + val io = IO(new Bundle { + val u = Input(UInt.width( 5)) + val b = Output(Bool()) + }) io.b := io.u.toBool } diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index 9ff8ed46..0d5a2188 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -2,10 +2,13 @@ package chiselTests -import Chisel._ import org.scalatest._ import org.scalatest.prop._ -import Chisel.testers.BasicTester + +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ +//import chisel3.core.ExplicitCompileOptions.Strict class ValueTester(w: Int, values: List[Int]) extends BasicTester { val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error? @@ -29,7 +32,7 @@ class TabulateTester(n: Int) extends BasicTester { class ShiftRegisterTester(n: Int) extends BasicTester { val (cnt, wrap) = Counter(Bool(true), n*2) - val shifter = Reg(Vec(n, UInt(width = log2Up(n)))) + val shifter = Reg(Vec(n, UInt.width(log2Up(n)))) (shifter, shifter drop 1).zipped.foreach(_ := _) shifter(n-1) := cnt when (cnt >= UInt(n)) { @@ -41,32 +44,6 @@ class ShiftRegisterTester(n: Int) extends BasicTester { } } -class FunBundle extends Bundle { - val stuff = UInt(width = 10) -} - -class ZeroModule extends Module { - val io = new Bundle { - val mem = UInt(width = 10) - val interrupts = Vec(2, Bool()).asInput - val mmio_axi = Vec(0, new FunBundle) - val mmio_ahb = Vec(0, new FunBundle).flip - } - - io.mmio_axi <> io.mmio_ahb - - io.mem := UInt(0) - when (io.interrupts(0)) { io.mem := UInt(1) } - when (io.interrupts(1)) { io.mem := UInt(2) } -} - -class ZeroTester extends BasicTester { - val foo = Module(new ZeroModule) - foo.io.interrupts := Vec.tabulate(2) { _ => Bool(true) } - assert (foo.io.mem === UInt(2)) - stop() -} - class VecSpec extends ChiselPropSpec { property("Vecs should be assignable") { forAll(safeUIntN(8)) { case(w: Int, v: List[Int]) => @@ -81,8 +58,4 @@ class VecSpec extends ChiselPropSpec { property("Regs of vecs should be usable as shift registers") { forAll(smallPosInts) { (n: Int) => assertTesterPasses{ new ShiftRegisterTester(n) } } } - - property("Dual empty Vectors") { - assertTesterPasses{ new ZeroTester } - } } diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala index 99ec66a6..b8e3a154 100644 --- a/src/test/scala/chiselTests/VectorPacketIO.scala +++ b/src/test/scala/chiselTests/VectorPacketIO.scala @@ -2,8 +2,9 @@ package chiselTests -import Chisel._ -import Chisel.testers.BasicTester +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ /** * This test used to fail when assignment statements were @@ -18,7 +19,7 @@ import Chisel.testers.BasicTester * IMPORTANT: The canonical way to initialize a decoupled inteface is still being debated. */ class Packet extends Bundle { - val header = UInt(width = 1) + val header = UInt.width(1) } /** @@ -27,8 +28,8 @@ class Packet extends Bundle { * The problem does not occur if the Vec is taken out */ class VectorPacketIO(n: Int) extends Bundle { - val ins = Vec(n, new DeqIO(new Packet())) - val outs = Vec(n, new EnqIO(new Packet())) + val ins = Vec(n, chisel3.util.DeqIO(new Packet())) + val outs = Vec(n, chisel3.util.EnqIO(new Packet())) } /** @@ -37,10 +38,11 @@ class VectorPacketIO(n: Int) extends Bundle { */ class BrokenVectorPacketModule extends Module { val n = 4 - val io = new VectorPacketIO(n) + val io = IO(new VectorPacketIO(n)) /* the following method of initializing the circuit may change in the future */ - io.outs.foreach(_.init()) + io.ins.foreach(_.nodeq()) + io.outs.foreach(_.noenq()) } class VectorPacketIOUnitTester extends BasicTester { diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala index 012fc493..00b1e7de 100644 --- a/src/test/scala/chiselTests/VendingMachine.scala +++ b/src/test/scala/chiselTests/VendingMachine.scala @@ -1,13 +1,16 @@ // See LICENSE for license details. package chiselTests -import Chisel._ + +import chisel3._ +import chisel3.util._ class VendingMachine extends Module { - val io = new Bundle { - val nickel = Bool(dir = INPUT) - val dime = Bool(dir = INPUT) - val valid = Bool(dir = OUTPUT) } + val io = IO(new Bundle { + val nickel = Input(Bool()) + val dime = Input(Bool()) + val valid = Output(Bool()) + }) val c = UInt(5, width = 3) val sIdle :: s5 :: s10 :: s15 :: sOk :: Nil = Enum(UInt(), 5) val state = Reg(init = sIdle) diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala index a6572706..6dc2dbac 100644 --- a/src/test/scala/chiselTests/When.scala +++ b/src/test/scala/chiselTests/When.scala @@ -3,14 +3,17 @@ package chiselTests import org.scalatest._ -import Chisel._ -import Chisel.testers.BasicTester + +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ +//import chisel3.core.ExplicitCompileOptions.Strict class WhenTester() extends BasicTester { val cnt = Counter(4) when(Bool(true)) { cnt.inc() } - val out = Wire(UInt(width=3)) + val out = Wire(UInt.width(3)) when(cnt.value === UInt(0)) { out := UInt(1) } .elsewhen (cnt.value === UInt(1)) { @@ -32,7 +35,7 @@ class OverlappedWhenTester() extends BasicTester { val cnt = Counter(4) when(Bool(true)) { cnt.inc() } - val out = Wire(UInt(width=3)) + val out = Wire(UInt.width(3)) when(cnt.value <= UInt(0)) { out := UInt(1) } .elsewhen (cnt.value <= UInt(1)) { |