aboutsummaryrefslogtreecommitdiff
path: root/test/passes/resolve-genders
AgeCommit message (Expand)Author
2015-05-18First pass at a Verilog Backend. Not tested, but compiles and generates reaso...azidar
2015-05-18Big API Change. Pad is no longer supported. Widths of primops can be flexible...azidar
2015-04-28Instances are now male. Reworked lowering pass to be sane. chisel3/ModuleVec....azidar
2015-04-23Added new parser. Fixed all Tests. Added on-reset to parser, but don't correc...azidar
2015-04-20Fixed tests to use new execution arguments. Added and fixed chisel3 bugsazidar
2015-04-17Fixed bug in primop lowering during type inference. Added reduce instructions...azidar
2015-04-10Updated StanzaPatrick Li
2015-04-08Added test to show correctness of gender inference and loweringazidar
2015-04-08Fixed bug in lowering that incorrectly determined genders when subfieldedazidar
2015-03-27Corrected register init by adding initialization of registers pass after lowe...azidar
2015-03-12Switched bundles from gender to flipazidar
2015-03-10Finished resolve gendersazidar
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-27 10:48:48 +0000