Added new parser. Fixed all Tests. Added on-reset to parser, but don't correctly handle it in compiler.

6 files changed, 22 insertions, 22 deletions

diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir
index 931372cb..8cae8ba4 100644
--- a/test/passes/resolve-genders/accessor.fir
+++ b/test/passes/resolve-genders/accessor.fir
@@ -3,7 +3,7 @@
 ;CHECK: Resolve Genders
 circuit top :
    module top :
-      wire m : UInt(32)[10][10][10]
+      wire m : UInt<32>[10][10][10]
       wire i : UInt
       accessor a = m[i] ;CHECK: accessor a = m@<g:male>[i@<g:male>]@<g:male>
       accessor b = a[i] ;CHECK: accessor b = a@<g:male>[i@<g:male>]@<g:male>
diff --git a/test/passes/resolve-genders/bigenders.fir b/test/passes/resolve-genders/bigenders.fir
index 48987a9a..56029969 100644
--- a/test/passes/resolve-genders/bigenders.fir
+++ b/test/passes/resolve-genders/bigenders.fir
@@ -3,9 +3,9 @@
 ;CHECK: Resolve Genders
 circuit top :
    module M :
-      input i : UInt(10)
-      output o : UInt(10)
-      wire w : {x : UInt(10), flip y : UInt(10)}
+      input i : UInt<10>
+      output o : UInt<10>
+      wire w : {x : UInt<10>, flip y : UInt<10>}
       w.x := i
       w.y := i
       o := w.x
diff --git a/test/passes/resolve-genders/bulk.fir b/test/passes/resolve-genders/bulk.fir
index 491760b6..9688a71b 100644
--- a/test/passes/resolve-genders/bulk.fir
+++ b/test/passes/resolve-genders/bulk.fir
@@ -3,9 +3,9 @@
 ;CHECK: Resolve Genders
 circuit top :
    module source :
-      output bundle : { data : UInt(16), flip ready : UInt(1) }
+      output bundle : { data : UInt<16>, flip ready : UInt<1> }
    module sink :
-      input bundle : { data : UInt(16), flip ready : UInt(1) }
+      input bundle : { data : UInt<16>, flip ready : UInt<1> }
    module top :
       inst src of source
       inst snk of sink
diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir
index 44e0200f..b16c9b66 100644
--- a/test/passes/resolve-genders/gcd.fir
+++ b/test/passes/resolve-genders/gcd.fir
@@ -9,16 +9,16 @@ circuit top :
       z := sub-wrap(x, y)
       ;CHECK: z@<g:female> := sub-wrap-uu(x@<g:male>, y@<g:male>)
    module gcd :
-      input a : UInt(16)
-      input b : UInt(16)
-      input e : UInt(1)
-      output z : UInt(16)
-      output v : UInt(1)
+      input a : UInt<16>
+      input b : UInt<16>
+      input e : UInt<1>
+      output z : UInt<16>
+      output v : UInt<1>
       reg x : UInt
       reg y : UInt
 ; CHECK: reg x : UInt
-      x.init := UInt(0)
-      y.init := UInt(42)
+      on-reset x := UInt(0)
+      on-reset y := UInt(42)
       when gt(x, y) :
       ;CHECK: when gt-uu(x@<g:male>, y@<g:male>) :
          inst s of subtracter
@@ -40,8 +40,8 @@ circuit top :
       v := eq(v, UInt(0))
       z := x
    module top :
-      input a : UInt(16)
-      input b : UInt(16)
+      input a : UInt<16>
+      input b : UInt<16>
       output z : UInt
       inst i of gcd
       i.a := a
diff --git a/test/passes/resolve-genders/ports.fir b/test/passes/resolve-genders/ports.fir
index c1708631..3155dbcf 100644
--- a/test/passes/resolve-genders/ports.fir
+++ b/test/passes/resolve-genders/ports.fir
@@ -3,14 +3,14 @@
 ;CHECK: Resolve Genders
 circuit top :
    module source :
-      output data : UInt(16)
-      input ready : UInt(1)
+      output data : UInt<16>
+      input ready : UInt<1>
       data := UInt(16)
    module sink :
-      input data : UInt(16)
-      output ready : UInt(1)
+      input data : UInt<16>
+      output ready : UInt<1>
    module top: 
-      wire connect : { data : UInt(16), flip ready: UInt(1) }
+      wire connect : { data : UInt<16>, flip ready: UInt<1> }
       inst src of source         ;CHECK: inst src of source@<g:female>
       inst snk of sink           ;CHECK: inst snk of sink@<g:female>
       connect.data := src.data   ;CHECK: connect@<g:female>.data@<g:female> := src@<g:female>.data@<g:male>
diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir
index 77cf13b3..6abc411a 100644
--- a/test/passes/resolve-genders/subbundle.fir
+++ b/test/passes/resolve-genders/subbundle.fir
@@ -3,8 +3,8 @@
 ;CHECK: Lower To Ground
 circuit top :
    module M :
-      wire w : { flip x : UInt(10)}
-      reg r : { flip x : UInt(10)}
+      wire w : { flip x : UInt<10>}
+      reg r : { flip x : UInt<10>}
       w := r     ; CHECK r$x := w$x
       w.x := r.x ; CHECK w$x := r$x
 ; CHECK: Finished Lower To Ground