sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2016-08-15	Remove stanza (#231)	Adam Izraelevitz
2016-02-09	Changed stanza output of UInt/SInt to include widths. Made tests match accord...	azidar
2016-01-28	Added addw to working ir as an optimized verilog emission	azidar
2016-01-28	Updated all tests to pass	azidar
2016-01-25	Changed tests to pass with change to postfix of generated name	azidar
2016-01-16	Fixed a bunch of tests, and minor bugs	azidar
2016-01-16	WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl...	azidar
2016-01-16	New memory works with verilog. Slowly changing tests and fixing bugs.	azidar
2015-09-29	Fixed final bug. All tests pass. Accessors are a go.	azidar
2015-08-24	Changed all tests to use verilog backend.	azidar
2015-07-31	Updated tests to pipe from stderr to stdout	azidar
2015-07-30	Updated lots of tests so they pass. Found one bug in expand whens	azidar
2015-07-14	Added tests for clocks. Added remove scope and special chars passes. Added te...	azidar
2015-07-14	Pass most tests. The ones that do not pass are not expected to, yet	azidar
2015-05-27	Added external modules. Switched lower firrtl back to wire r; r := Register, ...	azidar
2015-05-20	Added Pad pass to flo.stanza, which pads widths to make := and primops strict...	azidar
2015-05-18	Big API Change. Pad is no longer supported. Widths of primops can be flexible...	azidar
2015-04-23	Added new parser. Fixed all Tests. Added on-reset to parser, but don't correc...	azidar
2015-04-20	Fixed tests to use new execution arguments. Added and fixed chisel3 bugs	azidar
2015-04-08	Fixed bug in lowering that incorrectly determined genders when subfielded	azidar
2015-03-18	Finished expand accessors and lower to ground	azidar