sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2016-08-15	Remove stanza (#231)	Adam Izraelevitz
2016-01-28	Updated all tests to pass	azidar
2016-01-25	Fixed support for muxes and nodes with passive aggregate types	azidar
2016-01-24	Fixed tests that broke from changing verilog backend and removing mask from w...	azidar
2016-01-16	Finished first cut at new firrtl - time for testing! Chirrtl requires masks t...	azidar
2016-01-16	Fixed a bunch of tests, and minor bugs	azidar
2016-01-16	New memory works with verilog. Slowly changing tests and fixing bugs.	azidar
2015-08-24	Changed all tests to use verilog backend.	azidar
2015-07-31	Updated tests to pipe from stderr to stdout	azidar
2015-07-14	Added tests for clocks. Added remove scope and special chars passes. Added te...	azidar
2015-07-14	Pass most tests. The ones that do not pass are not expected to, yet	azidar
2015-05-27	Added sequential memories. mem no longer exists, must declare either cmem or ...	azidar
2015-05-19	Updated tests	azidar
2015-05-15	Updated firrtl for its passes to be a bit more modular, and to enable pluggin...	azidar
2015-04-29	Fixed bug where a node's width was not equal to its value's	azidar
2015-04-23	Added new parser. Fixed all Tests. Added on-reset to parser, but don't correc...	azidar
2015-04-22	Switched to stricter primop width constraints. Implemented Pad. Added some mi...	azidar
2015-04-20	Fixed tests to use new execution arguments. Added and fixed chisel3 bugs	azidar
2015-04-17	Added temp elimination pass	azidar
2015-04-17	Fixed bug in primop lowering during type inference. Added reduce instructions...	azidar
2015-04-09	Added more 'fake' tests. infer-widths now collects constraints	azidar