sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2015-05-27	Added sequential memories. mem no longer exists, must declare either cmem or ...	azidar
2015-05-27	Added external modules. Switched lower firrtl back to wire r; r := Register, ...	azidar
2015-05-20	Added Pad pass to flo.stanza, which pads widths to make := and primops strict...	azidar
2015-05-18	Big API Change. Pad is no longer supported. Widths of primops can be flexible...	azidar
2015-05-15	Updated firrtl for its passes to be a bit more modular, and to enable pluggin...	azidar
2015-05-13	Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bug	azidar
2015-04-27	Added on-reset	azidar
2015-04-23	Added new parser. Fixed all Tests. Added on-reset to parser, but don't correc...	azidar
2015-04-20	Fixed tests to use new execution arguments. Added and fixed chisel3 bugs	azidar
2015-04-08	Finished expand whens. started infer widths. added pdf for people to view	azidar
2015-03-27	Corrected register init by adding initialization of registers pass after lowe...	azidar
2015-03-25	Finished expand-whens. Removed letrec also, a while ago	azidar
2015-03-25	Correctly do when expansion, minus enables and outputting lowered form	azidar
2015-03-23	Finished first two parts of expand-whens pass. Fixed inits by adding WRegInit...	azidar
2015-03-18	Finished expand accessors and lower to ground	azidar