| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-09-16 | Change to Apache 2.0 License (#1901) | Chick Markley |
| 2020-07-27 | Update RightShiftTests.fir to avoid buggy Counter pattern | Albert Magyar |
| 2018-06-28 | Protobuf (#832) | Jack Koenig |
| 2017-06-27 | Emitting reg update mux tree, only walk netlist for wires and nodes | Jack Koenig |
| 2016-12-08 | Clk2clock - rename the implicit "clk" module input "clock" (#387) | Jim Lawson |
| 2016-08-17 | Change RW port names (#236) | Angie Wang |
| 2016-05-24 | Add integration test for single-ported memory | jackkoenig |
| 2016-03-15 | Revamp string literal handling | jackkoenig |
| 2016-03-10 | Add support for right shift by amount larger than argument width | jackkoenig |
| 2016-03-03 | Add some integration tests: successful compilation and execution | jackkoenig |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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