Change to Apache 2.0 License (#1901)

4 files changed, 6 insertions, 4 deletions

diff --git a/test/integration/GCDTester.fir b/test/integration/GCDTester.fir
index f236ecdc..2d4f479b 100644
--- a/test/integration/GCDTester.fir
+++ b/test/integration/GCDTester.fir
@@ -1,4 +1,5 @@
-circuit GCDTester : 
+; SPDX-License-Identifier: Apache-2.0
+circuit GCDTester :
   module DecoupledGCD : 
     input clock : Clock
     input reset : UInt<1>
diff --git a/test/integration/MemTester.fir b/test/integration/MemTester.fir
index f3d04be4..68e08544 100644
--- a/test/integration/MemTester.fir
+++ b/test/integration/MemTester.fir
@@ -1,4 +1,4 @@
-
+; SPDX-License-Identifier: Apache-2.0
 circuit MemTester :
   module ReadWrite :
     input clock : Clock
diff --git a/test/integration/PipeTester.fir b/test/integration/PipeTester.fir
index 3ca2f001..44c33774 100644
--- a/test/integration/PipeTester.fir
+++ b/test/integration/PipeTester.fir
@@ -1,4 +1,4 @@
-
+; SPDX-License-Identifier: Apache-2.0
 circuit PipeTester :
   ; This module should simply delay a signal by 2 cycles
   ; Internal registers reset to 0
diff --git a/test/integration/RightShiftTester.fir b/test/integration/RightShiftTester.fir
index d85757b8..92c4bb9e 100644
--- a/test/integration/RightShiftTester.fir
+++ b/test/integration/RightShiftTester.fir
@@ -1,4 +1,5 @@
-circuit RightShiftTester : 
+; SPDX-License-Identifier: Apache-2.0
+circuit RightShiftTester :
   module RightShift : 
     input clock : Clock
     input reset : UInt<1>