| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-07-14 | Added tests for clocks. Added remove scope and special chars passes. Added ↵ | azidar | |
| tests. Made more tests pass | |||
| 2015-07-14 | Pass most tests. The ones that do not pass are not expected to, yet | azidar | |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. ↵ | azidar | |
| Added Long support so UInt(LARGENUMBER) works | |||
| 2015-05-27 | Added sequential memories. mem no longer exists, must declare either cmem or ↵ | azidar | |
| smem. Added firrtl-gensym utility to generate a hashmap of names | |||
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar | |
| 2015-05-20 | Added Pad pass to flo.stanza, which pads widths to make := and primops ↵ | azidar | |
| strict. Have not tested this | |||
| 2015-05-05 | Added a bunch of tests. In the middle of implementing check kinds and check ↵ | azidar | |
| types. Does not compile | |||
| 2015-05-02 | Added a infrastructure for check passes, and wrote a few | azidar | |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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