| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. ↵ | azidar | |
| Added Long support so UInt(LARGENUMBER) works | |||
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar | |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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