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Add support for ProtoBuf serialization and deserialization
* Add support for additional features in .proto description
Features added: Info, Fixed[Type|Literal], AnalogType, Attach, Params
* Add support for .pb input files
This involves an API change where FIRRTL no longer implicitly adds .fir
to input file names
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This fixes --infer-rw to not expect an argument. After the annotations
refactor, no option was required, but some legacy code remained.
This also updates the test cases to be more correct and not specify an
option to --infer-rw.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Update Parser to use ANTLR CharStreams
This removes some unnecessary object creation in String reading and
manipulation
* Remove two unnecessary traversals from Block construction in Visitor
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Relying on /tmp as a place for test output will fail on multiuser systems and may fail if multiple instances of tests are running for the same user.
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Candidate fix for #749
This adds DefRegister netlist ordering to RemoveWires
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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It does not provide anything over NoTargetAnnotation. Its existence
suggests some significance so removing it for clarity.
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Escape raw params using \'
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Also minor cleanup to literal construction in Visitor
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Useful if you want to find out how a node was reachable and you used a blacklist during the reachability analysis
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Add optional argument to verilogToCpp to suppress VCD
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This enables the pattern of attaching "through" a wire to give better
Verilog that also works in Verilator
Use WrappedExpression when combining attaches in ExpandWhens
to ensure no duplication of references in resulting, combined attaches
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* Collects Infos found for symbols
* Merges multiple sources for symbol into MultiInfo
* Restores these Infos on connect statements.
* Add test showing preserved Infos
* Changed ++ methods on the Info sub-classes
* Ignore NoInfo being added
* Fixed way adding was implemented in MultiInfo
* Made InfoMap a class which defines the default value function
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* Make VerilogEmitter properly handle pad of width <= width of arg
* Constant prop pads with pad amount <= width of arg
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This should close #757. It should also allow for stop() and printf()
to be used with zero-width fields.
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Replaces old VerilogWrap which didn't work with split expressions and was
actually buggy anyway. This functionality reduces unnecessary intermediates in
emitted Verilog.
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* top wiring transform
* fixup comments
* TopWiring cosmetics
* move prefix into TopWiringAnnotation
* remove test function from transform file
* add ChildrenMap to InstanceGraph API
* use namespaces
* remove wiringUtils from TopWiring pass
* enable multiple output functions
* TopWiring cosmetics, tests and lowform
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The following are deprecated in favor of DiGraph/InstanceGraph:
- firrtl.passes.wiring.Lineage
- firrtl.passes.wiring.WiringUtils.ChildrenMap
- firrtl.passes.wiring.WiringUtils.getChildrenMap
- firrtl.passes.wiring.WiringUtils.getLineage
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Change VerilogMemDelays to put new Statements at end of Module
Fixes #547
This is instead of putting them right after the modified DefMemory which could
result in use before declaration errors for things that feed into the new
logic.
* Adds tests that show VerilogMemDelays crashing. (#792)
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* Cleaning up BlackBoxSourceHelper - use absolute file paths.
```bash
make[1]: *** No rule to make target `test_run_dir/examples.AccumBlackBox_PeekPokeTest_Verilator345491158/AccumBlackBox.v', needed by `/Users/john/chisel-testers/test_run_dir/examples.AccumBlackBox_PeekPokeTest_Verilator345491158/VAccumBlackBoxWrapper.h'. Stop.
```
since the path `test_run_dir/examples.AccumBlackBox_PeekPokeTest_Verilator345491158/AccumBlackBox.v` does not exist inside `test_run_dir`.
We should either:
- strip the targetDir prefix,
- prepend a `../` to the path,
- use absolute paths
I decided to go with the latter since this makes the least assumptions about the actual downstream processing and we already use absolute paths in other parts of this code.
* Minor cleanup.
- Anonymize make failure comment.
- Use common map syntax.
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h/t @sdtwigg
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Create sources once per module, not once per instance
Clean up writing the file list
Don't prepend file list with '-v's (non-standard and not all verilog)
Change file list file name (not all verilog)
Use ListSets for determinism
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Also make DiGraphTests more ScalaTest-y
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It wasn't properly padding the width of the constant zero.
Also add a test that shows the buggy behavior.
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Needed for special handling in Treadle.
Small refactor that allows users of DiGraph#linearize
to return the first node found in a cycle.
Fixed RemoveWiresTransfrom to handle this.
Added test to show usage of this feature.
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Also delete CircuitTopName. It will not work with updated RenameMap
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Moved from RemoveValidIf
Also Make RemoveValidIf.getGroundZero public and support Fixed
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Improve constant propagation of connections to references
[skip formal checks]
LEC fails on this PR because this PR actually changes the circuit. The
change is that it constant propagates some additional registers. This is
really just extending #621 to work on more registers that it was
supposed to be propagating anyway.
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* Make WiringTransform remove its used annotations
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Propagate exceptions from JsonProtocol deserialization
* Add AnnotationFileNotFoundException for better error reporting
* Add AnnotationClassNotFoundException for better error reporting
* Better propagate JSON parsing errors
Also report the file if there is a error deserializing a JSON file
* Make exception for non-array JSON file more explicit
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* Added grouping pass
* Added InfoMagnet and infomappers
* Changed return type of execute to allow final CircuitState inspection
* Updated dedup. Now is name-agnostic
* Added GroupAndDedup transform
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Also make ParserException extend FIRRTLException to better report parsing
errors to the user
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* Adding the firrtl proto.
* .
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* Pass up annotations in return value from Driver.execute
Backward compatible with existing usage.
Adds CircuitState to FirrtlExecutionSuccess, but
that member is not part of the unapply.
"To a single file per module if OneFilePerModule is specified"
test shows example of getting access to annotations
* As experiment return created files in annotations
Fix line missed in last push
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Closes #666.
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Large amounts of Wiring could result in huge nesting of Statements. This could
cause stack overflows using the Mappers. Fixed by no longer nesting Statements
in Wiring Pass.
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Also make InvalidAnnotationFileException extend FIRRTLException for better
error reporting
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Use the standard convention of 'XxYyException' for the previously named
LsbLargerThanMsb Exception.
h/t @kevintownsend
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- Old Annotation renamed to deprecated LegacyAnnotation
- Annotation is now a trait that can be extended
- New JsonProtocol for Annotation [de]serialization
- Replace AnnotationMap with AnnotationSeq
- Deprecate Transform.getMyAnnotations
- Update Transforms
- Turn on deprecation warnings
- Remove deprecated Driver.compile
- Make AnnotationTests abstract with Legacy and Json subclasses
- Add functionality to convert LegacyAnnotations of built-in annos
This will give a noisy warning and is more of a best effort than a
robust solution.
Fixes #475 Closes #609
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This makes the API change explicit. Also reintroduce loadAnnotations as
a deprecated function.
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* Add DiGraph sum and DiGraph sum test
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Make DiGraph sum deterministic
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Remove ordered hashes/sets from DiGraphTests
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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