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AgeCommit message (Expand)Author
2020-01-28add IsModule, IsMember, CompleteTarget serializers (#1321)Albert Chen
2020-01-21Refactoring checkCatArgumentLegality (#1317)Derek Pappas
2020-01-20clean up warnings: trim unused imports (#1315)John Ingalls
2020-01-15Verilog emitter transform InlineBitExtractions (#1296)John Ingalls
2020-01-15improve the tail ir usability. (#1241)Sequencer
2020-01-15Filter ResolvePaths in EliminateTargetPaths (#1310)Schuyler Eldridge
2020-01-10Change LoggerState.globalLevel to Warn (#1307)Jim Lawson
2020-01-10Change default LogLevel to Warn (#1305)Schuyler Eldridge
2020-01-09Dedup PassTests, add NoCircuitDedupAnnotations (#1302)Schuyler Eldridge
2020-01-07Change printing of FIRRTL runtime from error to warnJack Koenig
2020-01-07Remove printlns from testsJack Koenig
2020-01-07Switch compileFirrtlTest from Driver to FirrtlStageJack Koenig
2020-01-07Redirect testing shell commands to loggerJack Koenig
2020-01-07Fix literals cast to Clocks in Print and StopJack Koenig
2020-01-07Remove unnecessary $signed casts for PrimOps in Verilog EmitterJack Koenig
2020-01-07Remove unnecessary casts in Constant PropagationJack Koenig
2020-01-06Verilog emitter transform InlineNots (#1270)John Ingalls
2020-01-06Remove incorrect --firrtl-source option (#1266)Schuyler Eldridge
2020-01-06Make EmittedAnnotation Unserializable (#1288)Schuyler Eldridge
2019-12-30Minor code cleansup in InferResetsJack Koenig
2019-12-30Respect last connect semantics in InferResetsJack Koenig
2019-12-18Improve Scaladoc (#1284)Schuyler Eldridge
2019-12-18Fix incorrect ScalaDoc link (#1282)Schuyler Eldridge
2019-12-16{Firrtl, Circuit}Option should be Unserializable (#1278)Schuyler Eldridge
2019-12-11Make the member 'logger' added by the trait LazyLogging protected. (#1271)Jim Lawson
2019-12-06Move --no-dedup from stage-global to firrtl-local (#1265)Schuyler Eldridge
2019-12-03Logger tweaks (#1190)edwardcwang
2019-11-29Remove scala-logging fully in favor of our own loggerJack Koenig
2019-11-19Error when blackboxing memories with unsupported masking (#1238)Abraham Gonzalez
2019-11-18Make updated type info available in VerilogMemDelays (#1243)Albert Magyar
2019-11-14Use getName instead of getSimpleNameSchuyler Eldridge
2019-11-14Add test with Transform inside objectSchuyler Eldridge
2019-11-07Add check for multiple sources for same wiring pin (#1191)Jack Koenig
2019-11-05Move CheckResets after CheckCombLoops (#1224)Jack Koenig
2019-11-04Merge branch 'master' into serialization-utilsJack Koenig
2019-11-04Ignore extmodule instances in Flatten (#1218)Albert Magyar
2019-11-04Add explicit EOF to top-level parser rule (#1217)Albert Magyar
2019-10-31Guard initial blocks in emitted Verilog with `ifndef SYNTHESISJack Koenig
2019-10-30Add some simple tests to demonstrate how to provide type hintsDavid Biancolin
2019-10-29Remove an unneeded castDavid Biancolin
2019-10-29Some cleanupDavid Biancolin
2019-10-29Update src/main/scala/firrtl/annotations/JsonProtocol.scalaDavid Biancolin
2019-10-29Check that all annotations provide the typeHintDavid Biancolin
2019-10-29Try implementing recursive typeHint look upDavid Biancolin
2019-10-29Change findInstancesInHierarchy to return implicit top instanceAlbert Magyar
2019-10-25Only emit the DeserilizationTypeHintsAnno when neededDavid Biancolin
2019-10-24Enhance CheckCombLoops errors with connection infoAlbert Magyar
2019-10-24Add EdgeData trait to mix in to graphsAlbert Magyar
2019-10-24Supply a trait to allow user annotations to provide SERDES type hintsDavid Biancolin
2019-10-22Add Register Updates/else-if Verilog Emitter testsSchuyler Eldridge
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