diff options
| author | Jack Koenig | 2019-11-05 09:39:50 -0800 |
|---|---|---|
| committer | mergify[bot] | 2019-11-05 17:39:50 +0000 |
| commit | 5f59427f13b06ad2ad01e4b9b35a7c210f21a5f2 (patch) | |
| tree | a2270a654d969f6404d0a367584b16f8172f7233 /src | |
| parent | d4087a93f17612a6015eafc90a513dfd24b49f54 (diff) | |
Move CheckResets after CheckCombLoops (#1224)
Recursive literal lookup needs to be guarded against combinational loops
Added a test-case to illustrate the issue when CheckResets is run before CheckCombLoops
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 2 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/AsyncResetSpec.scala | 16 |
2 files changed, 17 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index 75645319..0d9b971b 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -71,7 +71,6 @@ class HighFirrtlToMiddleFirrtl extends CoreTransform { passes.ResolveKinds, passes.InferTypes, passes.CheckTypes, - new checks.CheckResets, passes.ResolveFlows, new passes.InferWidths, passes.CheckWidths, @@ -97,6 +96,7 @@ class MiddleFirrtlToLowFirrtl extends CoreTransform { passes.Legalize, new firrtl.transforms.RemoveReset, new firrtl.transforms.CheckCombLoops, + new checks.CheckResets, new firrtl.transforms.RemoveWires) } diff --git a/src/test/scala/firrtlTests/AsyncResetSpec.scala b/src/test/scala/firrtlTests/AsyncResetSpec.scala index 8ad397b3..ed90954b 100644 --- a/src/test/scala/firrtlTests/AsyncResetSpec.scala +++ b/src/test/scala/firrtlTests/AsyncResetSpec.scala @@ -231,6 +231,22 @@ class AsyncResetSpec extends FirrtlFlatSpec { result should containLine ("always @(posedge clock or posedge reset) begin") } + "CheckResets" should "NOT raise StackOverflow Exception on Combinational Loops (should be caught by firrtl.transforms.CheckCombLoops)" in { + an [firrtl.transforms.CheckCombLoops.CombLoopException] shouldBe thrownBy { + compileBody(s""" + |input clock : Clock + |input reset : AsyncReset + |wire x : UInt<1> + |wire y : UInt<2> + |x <= UInt<1>("h01") + |node ad = add(x, y) + |node adt = tail(ad, 1) + |y <= adt + |reg r : UInt, clock with : (reset => (reset, y)) + |""".stripMargin + ) + } + } "Every async reset reg" should "generate its own always block" in { val result = compileBody(s""" |
