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(#2091)
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* firrtl: add optional statement labels for stop, printf, assert, assume and cover
* test: parsing of statement labels
* ir: ensure that name is properly retained
* SymbolTable: add support for labled statements
* test: parsing statement labels
* test: lower types name collisions with named statements
* ignore empty names
* Inline: deal with named and unnamed statements
* RemoveWires: treat stop, printf and verification statements as "others"
* test: fix InlineInstance tests
* DeadCodeEliminations: statements are now als declarations
* CheckHighForm: ensure that statement names are not used as references
* CheckSpec: throw error if statement name collides
* add pass to automatically add missing statement names
* check: make sure that two statements cannot have the same name
* stmtLabel -> stmtName
* scalafmt
* add statement names to spec
* spec: meta data -> metadata
* EnsureStatementNames: explain naming algorithm
* remove returns
* better namespace use
* ir: add CanBeReferenced trait
* ir: add newline as jack requested
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This enables marking modules as "must deduplicate". If modules marked as
such do not deduplicate, the transform will create error reports and
make suggestions as to why deduplication failed.
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* New factory method enables direct construction of DiGraphs from edges
* DiGraph.prettyTree enables visualization of tree or multi-tree
diagraphs
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* build: add data-class dependency
* ir: turn Print, Stop and Verification nodes into data classes
This is in preparation to add a name field to them.
Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
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* Add SubAccess case to Utils.splitRef
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Update Utils.splitRef to use IR types
Change Utils.splitRef to use the actual IR types instead of their
WIR aliases. Update the Scaladoc note to reflect this.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Deprecate firrtl.passes.ToWorkingIR
Deprecate ToWorkingIR as it is now an identity transform.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Deprecate firrtl.stage.Forms.WorkingIR
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Switch from Forms.WorkingIR to Forms.MinimalHighForm
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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This allows ConstantPropagation to be used in cases where
ValidIfs need to be maintained, e.g., in the formal backend.
Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Fixes bug with mul or div followed by cat.
Also fixes some Verilog lint issues.
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* Check Unidoc on all versions of Scala
It is required for publishing and we publish every version
* Fix conflicting cross-version suffixes issue
When running `sbt ++2.13.4 unidoc`, SBT would set the Scala version
for the fuzzer and benchmark projects even though they aren't really
relevant to the command. This may be a misconfiguration or a bug in
the unidoc plugin. Whatever the case, simply making it possible for
them to use the same version of Scala as the firrtl project (on which
they depend) fixes the issue.
* Match versions of Scala in build.sbt and CI
* Fix unidoc issues in 2.13.4
There is some bug in ScalaDoc not finding some links in firrtl.options
so those links were made absolute as a workaround.
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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This adds a --dont-fold options (backed by a DisableFold annotation)
that lets a user specify primitive operations which should never be
folded. This feature lets a user disable certain folds which may be
allowable in FIRRTL (or by any sane synthesis tool), but due to inane
Verilog language design causes formal equivalence tools to fail due to
the fold.
Add a test that a user can disable `a / a -> 1` with a
DisableFold(PrimOps.Div) annotation.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Fix scalafmtCheckAll failures that snuck through
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This is done by having LowerTypes uses two RenameMaps instead of one for
each module. There is one for renaming instance paths, and one for
renaming everything within modules.
Also add some utilities:
* TargetUtils for dealing with InstanceTargets
* RenameMap.fromInstanceRenames
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* add test for RemoveAccessesSpec.
* fix nested SubAccess bug.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Add SortModules to transform to def-before-use
Adds a new transform, SortModules, that transforms a FIRRTL circuit
to enforce an invariant of modules and external modules being defined
before use. This transform is left as optional in the event that a
user may wish to have a quick way of getting the circuit to respect
this property as may be expected of some other tool, e.g., MLIR.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Add test of SortModules transform
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Verilator 4.034 was complaining about wires being named weak and strong
because those are SV 2009 keywords. Added them to the Utils.v_keywords list
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* Make MultiTargetAnnotation.targets a def
This enables the annotation writer to choose their own underlying data structure
* Update MultiTargetAnnotation ScalaDoc
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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It would replace them with a validif node with a UIntLiteral which can
lead to type errors.
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* smt: add test for write port collision
* smt: add missing call to insertDummyAssignsForMemoryOutputs
* smt: fix typo in write port code
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* split big Emitter to submodules.
* fix all deprecated warning.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* smt: add tests for assert name clashes
* smt: ensure unique signal names with a namespace
this fixes issues #1934
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* Make Stage.run protected
Change the access modifier of Stage.run from no modifier to protected.
This method is really an internal API that the user implements with
the main entry point for a Stage being "execute" or "transform". By
allowing users to access "run" they can bypass checks, mandatory file
reads/writes, and wrappers.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Make FirrtlStage.run protected
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Overflow of 32-bit Int would cause any negative literal value equal to
-(2^(width % 32 - 1)) where width >= 32 to be incorrectly inverted
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* Also clean up VerilogMemDelaySpec structure
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Also speed up common case of Array[Byte]
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Both use EliminateTargetPaths to duplicate modules based on annotations.
Currently, EliminateTargetPaths API is a little too limited so it
duplicates more than it should which effectively breaks Dedup whenever
DontTouchAnnotations are present.
Also, make ConstProp and DCE treat all HasDontTouches as local
annotations even if they are instance annotations. This is more
conservative but it is generally better to preserve deduplication than
to maximally optimize every instance.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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These options are generally specific to a stage and thus should not be
propagating across serialization
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* test multiinfo comparison and mux cond inlining
* loosen inlining conditions
* fix typo
* include dshlw
* fix test
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Also rename --Wno-scala-version-warning to
--warn:no-scala-version-deprecation and adopt naming convention where
resulting annotation matches the CLI option
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* InlineBooleanExpressions: test DontTouch
* run scalafmt
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