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2020-08-06Add deprecations for more firrtl.Compiler methods (#1791)Schuyler Eldridge
Adds missing deprecation warnings to firrtl.Compiler methods: compile and compileAndEmit. This provides a more informative message to the user about how to actually migrate. Without this, the user only has the generic deprecation warning about class Compiler. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-08-05ir: add UseSerializer mixin trait (#1824)Kevin Laeufer
Using the new trait to overwrite serialize at the leaf classes, we ensure that new, e.g., Expression nodes will not automatically try to call `Serializer.serialize` which would fail by default. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-08-05Deprecate InstanceGraph (#1800)Kevin Laeufer
* InstanceKeyGraph: add staticInstanceCount, getGraph and getChildrenInstanceMap * InstanceKeyGraph: reachableModules, unreachableModules, lowestCommonAncestor and fullHierarchy * Replace usage of InstanceGraph with InstanceKeyGraph Also deprecates all unused methods. * WiringUtils: make new version of sinksToSources package private This will make our live easier next time we need to change it. * CircuitGraph: use InstanceKeyGraph * InstanceKeyGraphSpec: respect maximum line width * InstanceKeyGraph: make constructor private * InstanceKeyGraph: move lowestCommonAncestor function to Wiring * WiringUtils: update deprecation message
2020-08-01Error on ExtModules w/ same defname, diff. ports (#1734)Schuyler Eldridge
* Use signed output in LargeParamExecutionTest Change the Verilog used in LargeParamExecutionTest to match its ExtModule specification. An ExtModule with an SInt port should map to a separate Verilog module with a signed port and this is disjoint from an ExtModule with a UInt port. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Error on ExtModules w/ same defname, diff. ports Adds a high form check to ensure that external modules that have the same defname also have exactly the same ports. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-31Avoid repeated inlining in FlattenRegUpdate (#1727)Jack Koenig
* Avoid repeated inlining in FlattenRegUpdate When-else structure can lead to the same complex mux structure being the default on several branches in register update logic. When these are inlined, it can lead to artifical unreachable branches that show up as coverage holes in coverage of the emitted Verilog. This commit changes the inlining logic to prevent inlining any reference expression that shows up multiple times because this is a common indicator of the problematic case. * Add tests for improved register update logic emission * Improve FlattenRegUpdate comment and add more tests * [skip formal checks] ICache equivalence check verified locally
2020-07-31CircuitGraph: remove fields from public API (#1813)Kevin Laeufer
They are never used outside of the class not even in tests.
2020-07-31[WIP] Implement CircuitGraph and IRLookup to firrtl.analyses (#1603)Jiuyang Liu
* WIP Commit * Add EdgeDataDiGraph with views to amortize graph construction * WIP, got basic structure, need tests to pipeclean * First tests pass. Need more. * Tests pass, more need to be written * More tests pass! Things should work, except for memories * Added clearPrev to fix digraph uses where caching prev breaks * Removed old Component. Documented IRLookup * Added comments. Make prev arg to getEdges * WIP: Refactoring for CircuitGraph * Refactored into CircuitGraph. Can do topological module analysis * Removed old versions * Added support for memories * Added cached test * More stufffff * Added implicit caching of connectivity * Added tests for IRLookup, and others * Many major changes. Replaced CircuitGraph as ConnectionGraph Added CircuitGraph to be top-level user-facing object ConnectionGraph now automatically shortcuts getEdges ConnectionGraph overwrites BFS as PriorityBFS Added leafModule to Target Added lookup by kind to IRLookup Added more tests * Reordered stuff in ConnectionGraph * Made path work with deep hierarchies. Added PML for IllegalClockCrossings * Made pathsInDAG work with current shortcut semantics * Bugfix: check pathless targets when shortcutting paths * Added documentation/licenses * Removed UnnamedToken and related functionality * Added documentation of ConnectionGraph * Added back topo, needed for correct solving of intermediate modules * Bugfix. Cache intermediate clockSources from same BFS with same root, but not BFS with different root * Added literal/invalid clock source, and unknown top for getclocksource * Bugfix for clocks in bundles * Add CompleteTargetSerializer and test * remove ClockFinder, be able to compile. * test is able to compile, but need to fix. * public and abstract DiGraph, remove DiGraphLike. * revert some DiGraph code, ConnectionGraphSpec passed. * CircuitGraphSpec passed. * minimize diff between master * codes clean up * override linearize and revert DiGraph * keep DiGraph unchanged. * make ci happy again. * codes clean up. * bug fix for rebase * remove wir * make scaladoc happy again. * update for review. * add some documentation. * remove tag * wip IRLookup * code clean up and add some doucmentations. * IRLookup cache with ModuleTarget guarded. * make unidoc and 2.13 happy Co-authored-by: Adam Izraelevitz <azidar@gmail.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-07-30ir: use Serializer.serialize where possible (#1809)Kevin Laeufer
* ir: use Serializer.serialize where possible * ir.Serializer: serialize MultiInfo correctly * ir.Serializer: empty body needs to result in a skip statement The firrtl grammar requires at least one statement. * ir.Serializer: correctly serialize fixed point types and literals * Serializer: change Seq -> Iterable in order to be Scala 2.13 compatible
2020-07-29ManipulateNames: use composition instead of extending HashMapKevin Laeufer
2020-07-29[2.13] fix legacy procedure syntaxKevin Laeufer
2020-07-29[2.13] use scala.collection.Seq instead of mutable.SeqKevin Laeufer
2020-07-29PropagatePreset: use partition function to find other annotationsKevin Laeufer
2020-07-29[2.13] toSeq, Unit -> (), and postfix fixesKevin Laeufer
2020-07-29[2.13] Range.Double -> Range.BigDecimalKevin Laeufer
The values end up being converted to BigDecimal anyways.
2020-07-29[2.13] EmissionOptionMap now uses a HashMap instead of extending itKevin Laeufer
Extending HashMap is discouraged.
2020-07-29[2.13] replace `= Unit` with `= ()`Kevin Laeufer
2020-07-29Compiler: clarify package of DedupModulesKevin Laeufer
2020-07-29MemConf: build list of tuples and turn it into a map at the endKevin Laeufer
2020-07-29[2.13] convert toSeq and toMap where necessary to compileKevin Laeufer
2020-07-29[2.13] explicitly use a parallel vectorKevin Laeufer
2020-07-29WiringTransform: fix non-determinism (#1799)Kevin Laeufer
* WiringUtils.sinksToSources: make sinkInsts order deterministic * WiringUtils: make owners a LinkedHashMap * Wiring: only make something a Wire if it isn't a port already Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-29RemoveWires: improve dependencies and declare ResolveKinds as an ↵Kevin Laeufer
invalidation (#1797) Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-29InferTypes: fix bugs with unknown widths on ports and memories (#1769)Kevin Laeufer
* InferTypesFlowsAndKindsSpec: test the results of InferTypes, ResolveKinds and ResolveFlows * Don't use passes sub-package in tests This changes two test files using the "passes" sub-package to "firrtl.passes". This allows a new "firrtlTests.passes" package to be freely created and used without a name collision. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * ResolveFlows: only depends on types and working ir The types are needed to know the orientation of a bundle field of a SubField node. * InferTypes: fix bugs with unknown widths on ports and memories * LoweringCompileSpec: Uniquify pass moved Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-29RenameMapSpec: try rename instance and port (#1776)Kevin Laeufer
* RenameMapSpec: try rename instance and port * RenameMapSpec: explicit chaining is required Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-28Fix incorrect error message (#1795)Andrew Waterman
dshl amount must be < 20 bits, not <= 20 bits. Resolves #1794
2020-07-27Fix out-of-scope reference in handwritten CHIRRTL mem testAlbert Magyar
2020-07-27Add adapter to make current CHIRRTL mport scoping legalAlbert Magyar
* See #1505 * Inferred mports are implicitly added to scope of their parent mem * This allows current chisel3 emission to work with new scope checks * This may change in a future refactor of CHIRRTL memory ports
2020-07-27Add Conditionally scoping tests to CheckSpecAlbert Magyar
* Add specific test for shadowing
2020-07-27Honor block scoping of Conditionally in CheckHighFormAlbert Magyar
* Fixes #1505
2020-07-25Integrate new transforms with firrtl.stage.Forms (#1754)Schuyler Eldridge
Move new transforms, recently added, into existing or new sets of transforms (defined in firrtl.stage.Forms). One transform is a mandatory low FIRRTL optimization: - firrtl.transforms.LegalizeAndReductionsTransform Previously, this was included as a prerequisite of all Verilog emitters (minimum, normal, and SystemVerilog). Two transforms associated with converting and removing the new verification statements are moved into a new set of transforms, AssertsRemoved: - firrtl.transforms.formal.ConvertAsserts - firrtl.transforms.formal.RemoveVerificationStatements Previously, these transforms were directly added as prerequisites to the minimum Verilog and normal Verilog emitter, but not the SystemVerilog emitter. The designation of inputForm=LowForm for legacy, custom transforms is updated to include assertion removal transforms as part of their optionalPrerequisites. This has the effect of continuing to cause inputForm=LowForm transforms to run as late as possible (right before the low FIRRTL, minimum Verilog, Verilog, or SystemVeriog emitter). Tests are updated to reflect the new order in both CustomTransformSpec and LoweringCompilersSpec. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-24Fix sign extension issue in Emitter (#1785)Albert Chen
* add sign-extend const-prop test * Emitter: don't wrap Neg operand in concat
2020-07-23fix reduction op bug ConstantPropagation (#1746)Albert Chen
* add const prop bitwise reduction equivalence test * mask negative literals when propagating reduction * change widths * get rid of unnecessary if * add BigInt mask utility
2020-07-23mask bits when propagating bitwise ops (#1745)Albert Chen
* ConstProp: test bitwise op of signed literals * ConstProp: use bit mask for FoldOr/FoldXor * handle and also * add UIntLiteral.masked helper Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-07-23Update negative literal emission (#1782)Albert Chen
* test const prop of addition of negative literals * Emitter: handle minimum negative values correctly * update expected verilog in AsyncResetSpec
2020-07-20Make InferWidths thread safe (#1775)Schuyler Eldridge
Change the class-global, but private ConstraintSolver object inside InferWidths to instead be constructed on each execute invocation. This prevents issues with thread safety where running the same InferWidths object at the same time would cause the ConstraintSolver to get trampled on. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-18Faster dedup instance graph (#1732)Kevin Laeufer
* dedup: add faster InstanceGraph implementation and use it in dedup The new implementation takes care not to hash the instance types contained in DefInstance nodes. This should make dedup considerably faster. * FastInstanceGraph: cache vertices for faster findInstancesInHierarchy * FastInstanceGraph: remove the parent name field since it isn't actually necessary * FastInstanceGraph -> InstanceKeyGraph * InstanceGraph: describe performance problems. * InstanceKeyGraph: turn moduleMap into a def instead of a val This will make changing implementation details much easier in the future. * InstanceKeyGraph: return childInstances as Seq instead of Map This ensures a deterministic iteration order and it can easily be turned into a Map for O(1) accesses. * InstanceKeyGraph: add tests for public methods * InstanceKeyGraph: group public methods together * InstanceKeyGraphSpec: fix wording of a comment Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-17Propagate source locators to register update always blocks (#1743)Jack Koenig
* [WIP] Propagate source locators to Verilog if-else emission * Add and fix tests for reg update info propagation * Add limited source locator propagation in ConstProp Support propagating source locators on connections or nodes where the right-hand side is simply a reference. This case comes up a lot for registers without a synchronous reset. node _T_1 = x @[MyFile.scala 12:10] node _T_2 = _T_1 z <= x Previousy the source locator would be lost, now the result is: z <= x @[MyFile.scala 12:10] * Address review comments Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-16Simplify CustomTransformSpecSchuyler Eldridge
Refactor the test used in the CustomTransformSpec to assert that inputForm=LowForm legacy transforms run right before the emitter (see note below!). The new test looks only for a list of (customTransform, emitter) in a sliding, size-2 window of the flattened transform order. Previously, this was looking for a match before and after the custom transform. The old implementation necessitate busywork updates of the test when new transforms are added that changed the transform running before the custom transform. Note: this test, as written is intentionally wrong. When verification statements were added, the test was changed to not do what it's supposed to do. Namely, the test is supposed to ensure that an inputForm=LowForm transform runs immediately before its emitter. However, the test is actually checking that the custom transform runs before transforms that convert and remove verification statements. I'm intentionally leaving the test broken, but doing the refactor in order to make this easier to manually backport to the 1.3.x branch. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-07-16Remove overlapping inputForm=LowForm testsSchuyler Eldridge
Remove tests from LoweringCompilerSpec testing the placement of inputForm=LowForm legacy, custom transforms. This behavior is already tested in the CustomTransformSpec. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-07-15ir: store FileInfo string in escaped format (#1690)Kevin Laeufer
This should speed up the common case as the compiler never operates on the unescaped string. The new escape function also fixes a bug where ']' was not escaped even though it is the delimiting character for FileInfo. In order to maintain backwards compatibility for the ProtoBuf format, this patch adds escape/unescape calls when going from/to protobuf format. For better performance we should consider changing the protobuf format.
2020-07-14Make TopWiringTransform run before LowerTypes (#1750)Schuyler Eldridge
Add an optionalPrerequisiteOf to TopWiringTransform pointing at LowerTypes. This fixes a bug where top-wired wire bundles with flips could result in the top-wired, flattened bundle having every field with an "output" direction if the TopWiringTransform is moved around in the transform order (see FIRRTL issue #1744). Why did this happen? Fundamentally, this stems from the fact that LowerTypes preserves bundle direction for ports, but destroys it for wires. Specifically, The TopWiringTransform creates ports of the "output" direction that are copies of the underlying type of the component being top-wired. Before LowerTypes, the type of a bundle has direction information via flips. After LowerTypes, the lowered ground type does not have this information. Therefore, all the ports are ground type outputs. Simply ensuring that TopWiringTransform must run before LowerTypes avoids this problem. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-14Delete outdated scalastyle configuration comments from sourceAlbert Magyar
2020-07-14Fix parsing of info on multi-line registers (#1735)Jack Koenig
For multi-line registers, the parsed source locator is located in a different place in the concrete syntax tree than it is for other Statements. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-10Remove Left Over References to Gender in Code (#1752)Kevin Laeufer
* RemoveAccess: update gender to flow * ExpandWhens: update female to sink * RemoveCHIRRTL: female -> sink, male -> source
2020-07-08dedup: use structural sha256 hash instead of agnostify and serialize (#1731)Kevin Laeufer
* benchmark: add hot.DedupBenchmark * dedup: use structural md5 hash instead of agnostify and serialize * StructuralHash: generate PrimOp LUT * StructuralHash: change MessageDigestHasher to not be a case class * StructuralHash: we want Blocks and EmptyStmt to be ignored * StructuralHash: use SHA-256 instead of MD5 * StructuralHash: clarify extmodule port name agnistification * StructuralHash: hash the name of width vars instead of trying to agnostify This should be in line with the old Dedup behavior. The prior use of n(..) was incorrect since the namespace of these vars is different from the normal module scope namespace. * StructuralHash: address Schuyler's review comments Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-08ir: add faster serializer (#1694)Kevin Laeufer
This Serializer which is implemented external to the IR node definition uses a StringBuilder to achieve about a 1.7x performance improvement when serializing. Eventually, all implementations of the `serialize` methd should be replaced with a call to `Serializer.serialize`. However, for this PR we keep the old code in place in order to allow for easy regression testing with the benchmark JAR like this: > java -cp utils/bin/firrtl-benchmark.jar \ firrtl.benchmark.hot.SerializationBenchmark \ ~/benchmarks/medium.pb 2 5 test Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-07verification: emit mesage as Verilog comment (#1712)Kevin Laeufer
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-01Fix unchecked type in ManipulateNames (#1726)Schuyler Eldridge
Fix a bug where a type check would always yield true. This caused a bug where allow/block-list annotations would be incorrectly applied to all subtypes of ManipulateNames. The tests are updated to check that this now works. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-06-26Enable ConvertAsserts in default Verilog compilerAlbert Magyar
2020-06-26Add test for ConvertAssertsAlbert Magyar
* Add testcase for empty message
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