Remove Left Over References to Gender in Code (#1752)

* RemoveAccess: update gender to flow

* ExpandWhens: update female to sink

* RemoveCHIRRTL: female -> sink, male -> source

3 files changed, 30 insertions, 30 deletions

diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala
index 75aad29a..e7eebb57 100644
--- a/src/main/scala/firrtl/passes/ExpandWhens.scala
+++ b/src/main/scala/firrtl/passes/ExpandWhens.scala
@@ -121,22 +121,22 @@ object ExpandWhens extends Pass {
                     defaults: Defaults,
                     p: Expression)
                     (s: Statement): Statement = s match {
-      // For each non-register declaration, update netlist with value WVoid for each female reference
+      // For each non-register declaration, update netlist with value WVoid for each sink reference
       // Return self, unchanged
       case stmt @ (_: DefNode | EmptyStmt) => stmt
       case w: DefWire =>
-        netlist ++= (getFemaleRefs(w.name, w.tpe, DuplexFlow) map (ref => we(ref) -> WVoid))
+        netlist ++= (getSinkRefs(w.name, w.tpe, DuplexFlow) map (ref => we(ref) -> WVoid))
         w
       case w: DefMemory =>
-        netlist ++= (getFemaleRefs(w.name, MemPortUtils.memType(w), SourceFlow) map (ref => we(ref) -> WVoid))
+        netlist ++= (getSinkRefs(w.name, MemPortUtils.memType(w), SourceFlow) map (ref => we(ref) -> WVoid))
         w
       case w: WDefInstance =>
-        netlist ++= (getFemaleRefs(w.name, w.tpe, SourceFlow).map(ref => we(ref) -> WVoid))
+        netlist ++= (getSinkRefs(w.name, w.tpe, SourceFlow).map(ref => we(ref) -> WVoid))
         w
-      // Update netlist with self reference for each female reference
+      // Update netlist with self reference for each sink reference
       // Return self, unchanged
       case r: DefRegister =>
-        netlist ++= (getFemaleRefs(r.name, r.tpe, DuplexFlow) map (ref => we(ref) -> ref))
+        netlist ++= (getSinkRefs(r.name, r.tpe, DuplexFlow) map (ref => we(ref) -> ref))
         r
       // For value assignments, update netlist/attaches and return EmptyStmt
       case c: Connect =>
@@ -231,15 +231,15 @@ object ExpandWhens extends Pass {
     val netlist = new Netlist
     // Add ports to netlist
     netlist ++= (m.ports flatMap { case Port(_, name, dir, tpe) =>
-      getFemaleRefs(name, tpe, to_flow(dir)) map (ref => we(ref) -> WVoid)
+      getSinkRefs(name, tpe, to_flow(dir)) map (ref => we(ref) -> WVoid)
     })
     val bodyx = expandWhens(netlist, Seq(netlist), one)(m.body)
     (netlist, simlist, attaches, bodyx, infoMap)
   }
 
 
-  /** Returns all references to all Female leaf subcomponents of a reference */
-  private def getFemaleRefs(n: String, t: Type, g: Flow): Seq[Expression] = {
+  /** Returns all references to all sink leaf subcomponents of a reference */
+  private def getSinkRefs(n: String, t: Type, g: Flow): Seq[Expression] = {
     val exps = create_exps(WRef(n, t, ExpKind, g))
     exps.flatMap { case exp =>
       exp.tpe match {
diff --git a/src/main/scala/firrtl/passes/RemoveAccesses.scala b/src/main/scala/firrtl/passes/RemoveAccesses.scala
index d5615260..f571bf28 100644
--- a/src/main/scala/firrtl/passes/RemoveAccesses.scala
+++ b/src/main/scala/firrtl/passes/RemoveAccesses.scala
@@ -101,14 +101,14 @@ object RemoveAccesses extends Pass {
           (DefWire(get_info(s), n, e.tpe), WRef(n, e.tpe, kind(e), flow(e)))
         }
 
-        /** Replaces a subaccess in a given male expression
+        /** Replaces a subaccess in a given source expression
           */
         val stmts = mutable.ArrayBuffer[Statement]()
-        def removeMale(e: Expression): Expression = e match {
+        def removeSource(e: Expression): Expression = e match {
           case (_:WSubAccess| _: WSubField| _: WSubIndex| _: WRef) if hasAccess(e) =>
             val rs = getLocations(e)
             rs find (x => x.guard != one) match {
-              case None => throwInternalError(s"removeMale: shouldn't be here - $e")
+              case None => throwInternalError(s"removeSource: shouldn't be here - $e")
               case Some(_) =>
                 val (wire, temp) = create_temp(e)
                 val temps = create_exps(temp)
@@ -126,9 +126,9 @@ object RemoveAccesses extends Pass {
           case _ => e
         }
 
-        /** Replaces a subaccess in a given female expression
+        /** Replaces a subaccess in a given sink expression
           */
-        def removeFemale(info: Info, loc: Expression): Expression = loc match {
+        def removeSink(info: Info, loc: Expression): Expression = loc match {
           case (_: WSubAccess| _: WSubField| _: WSubIndex| _: WRef) if hasAccess(loc) =>
             val ls = getLocations(loc)
             if (ls.size == 1 & weq(ls.head.guard,one)) loc
@@ -142,30 +142,30 @@ object RemoveAccesses extends Pass {
           case _ => loc
         }
 
-        /** Recursively walks a male expression and fixes all subaccesses
+        /** Recursively walks a source expression and fixes all subaccesses
           * If we see a sub-access, replace it.
           * Otherwise, map to children.
           */
-        def fixMale(e: Expression): Expression = e match {
-          case w: WSubAccess => removeMale(WSubAccess(w.expr, fixMale(w.index), w.tpe, w.flow))
-          //case w: WSubIndex => removeMale(w)
-          //case w: WSubField => removeMale(w)
-          case x => x map fixMale
+        def fixSource(e: Expression): Expression = e match {
+          case w: WSubAccess => removeSource(WSubAccess(w.expr, fixSource(w.index), w.tpe, w.flow))
+          //case w: WSubIndex => removeSource(w)
+          //case w: WSubField => removeSource(w)
+          case x => x map fixSource
         }
 
-        /** Recursively walks a female expression and fixes all subaccesses
-          * If we see a sub-access, its index is a male expression, and we must replace it.
+        /** Recursively walks a sink expression and fixes all subaccesses
+          * If we see a sub-access, its index is a source expression, and we must replace it.
           * Otherwise, map to children.
           */
-        def fixFemale(e: Expression): Expression = e match {
-          case w: WSubAccess => WSubAccess(fixFemale(w.expr), fixMale(w.index), w.tpe, w.flow)
-          case x => x map fixFemale
+        def fixSink(e: Expression): Expression = e match {
+          case w: WSubAccess => WSubAccess(fixSink(w.expr), fixSource(w.index), w.tpe, w.flow)
+          case x => x map fixSink
         }
 
         val sx = s match {
           case Connect(info, loc, exp) =>
-            Connect(info, removeFemale(info, fixFemale(loc)), fixMale(exp))
-          case sxx => sxx map fixMale map onStmt
+            Connect(info, removeSink(info, fixSink(loc)), fixSource(exp))
+          case sxx => sxx map fixSource map onStmt
         }
         stmts += sx
         if (stmts.size != 1) Block(stmts) else stmts(0)
diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
index 8ba783ca..87a43ce3 100644
--- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
+++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
@@ -12,7 +12,7 @@ import firrtl.options.Dependency
 
 case class MPort(name: String, clk: Expression)
 case class MPorts(readers: ArrayBuffer[MPort], writers: ArrayBuffer[MPort], readwriters: ArrayBuffer[MPort])
-case class DataRef(exp: Expression, male: String, female: String, mask: String, rdwrite: Boolean)
+case class DataRef(exp: Expression, source: String, sink: String, mask: String, rdwrite: Boolean)
 
 object RemoveCHIRRTL extends Transform with DependencyAPIMigration {
 
@@ -190,9 +190,9 @@ object RemoveCHIRRTL extends Transform with DependencyAPIMigration {
           case SinkFlow =>
             has_write_mport = true
             if (p.rdwrite) has_readwrite_mport = Some(SubField(p.exp, "wmode", BoolType))
-            SubField(p.exp, p.female, tpe)
+            SubField(p.exp, p.sink, tpe)
           case SourceFlow =>
-            SubField(p.exp, p.male, tpe)
+            SubField(p.exp, p.source, tpe)
         }
         case None => g match {
           case SinkFlow => raddrs get name match {