[2.13] convert toSeq and toMap where necessary to compile

33 files changed, 87 insertions, 81 deletions

diff --git a/src/main/scala/firrtl/AddDescriptionNodes.scala b/src/main/scala/firrtl/AddDescriptionNodes.scala
index 1e17f5bd..0d804e63 100644
--- a/src/main/scala/firrtl/AddDescriptionNodes.scala
+++ b/src/main/scala/firrtl/AddDescriptionNodes.scala
@@ -233,9 +233,9 @@ class AddDescriptionNodes extends Transform with DependencyAPIMigration {
       // map field 2 (component name) -> field 3 (a list of Descriptions)
       _.groupBy(_._2).mapValues(_.map(_._3))
       // and then merge like descriptions (e.g. multiple docstrings into one big docstring)
-      .mapValues(mergeDescriptions))
+      .mapValues(mergeDescriptions).toMap)
 
-    (modMap, compMap)
+    (modMap.toMap, compMap.toMap)
   }
 
   def executeModule(module: DefModule, annos: Seq[Annotation]): DefModule = {
diff --git a/src/main/scala/firrtl/Driver.scala b/src/main/scala/firrtl/Driver.scala
index 2c43ae6b..c6842f52 100644
--- a/src/main/scala/firrtl/Driver.scala
+++ b/src/main/scala/firrtl/Driver.scala
@@ -212,7 +212,7 @@ object Driver {
     val phases: Seq[Phase] = {
       import DriverCompatibility._
       new PhaseManager(
-        Seq( Dependency[AddImplicitFirrtlFile],
+        List( Dependency[AddImplicitFirrtlFile],
              Dependency[AddImplicitAnnotationFile],
              Dependency[AddImplicitOutputFile],
              Dependency[AddImplicitEmitter],
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 3329cf9e..35682eed 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -126,7 +126,7 @@ sealed abstract class FirrtlEmitter(form: CircuitForm) extends Transform with Em
         case other => other.foreach(onStmt)
       }
       onStmt(mod.body)
-      modules.distinct
+      modules.distinct.toSeq
     }
     val modMap = circuit.modules.map(m => m.name -> m).toMap
     // Turn each module into it's own circuit with it as the top and all instantied modules as ExtModules
diff --git a/src/main/scala/firrtl/ExecutionOptionsManager.scala b/src/main/scala/firrtl/ExecutionOptionsManager.scala
index 2e3cd096..d21ccade 100644
--- a/src/main/scala/firrtl/ExecutionOptionsManager.scala
+++ b/src/main/scala/firrtl/ExecutionOptionsManager.scala
@@ -77,7 +77,7 @@ case class CommonOptions(
     }
   }
 
-  def toAnnotations: AnnotationSeq = (if (topName.nonEmpty) Seq(TopNameAnnotation(topName)) else Seq()) ++
+  def toAnnotations: AnnotationSeq = List() ++ (if (topName.nonEmpty) Seq(TopNameAnnotation(topName)) else Seq()) ++
     (if (targetDirName != ".") Some(TargetDirAnnotation(targetDirName)) else None) ++
     Some(LogLevelAnnotation(globalLogLevel)) ++
     (if (logToFile) { Some(LogFileAnnotation(None)) } else { None }) ++
@@ -312,7 +312,7 @@ extends ComposableOptions {
       StageUtils.dramaticWarning("User set FirrtlExecutionOptions.inferRW, but inferRW has no effect!")
     }
 
-    (if (inputFileNameOverride.nonEmpty) Seq(FirrtlFileAnnotation(inputFileNameOverride)) else Seq()) ++
+    List() ++ (if (inputFileNameOverride.nonEmpty) Seq(FirrtlFileAnnotation(inputFileNameOverride)) else Seq()) ++
       (if (outputFileNameOverride.nonEmpty) { Some(OutputFileAnnotation(outputFileNameOverride)) } else { None }) ++
       Some(CompilerAnnotation(compilerName)) ++
       Some(InfoModeAnnotation(infoModeName)) ++
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 0a067c04..a807b39f 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -299,7 +299,7 @@ object Utils extends LazyLogging {
       expr
     }
     onExp(expression)
-    ReferenceTarget(main, module, Nil, ref, tokens)
+    ReferenceTarget(main, module, Nil, ref, tokens.toSeq)
   }
    @deprecated("get_flip is fundamentally slow, use to_flip(flow(expr))", "1.2")
    def get_flip(t: Type, i: Int, f: Orientation): Orientation = {
@@ -358,7 +358,7 @@ object Utils extends LazyLogging {
       e
     }
     e map addKids
-    kids
+    kids.toSeq
   }
 
   /** Walks two expression trees and returns a sequence of tuples of where they differ */
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index 8bdab21b..502d021d 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -83,12 +83,12 @@ class Visitor(infoMode: InfoMode) extends AbstractParseTreeVisitor[FirrtlNode] w
   }
 
   private def visitCircuit(ctx: CircuitContext): Circuit =
-    Circuit(visitInfo(Option(ctx.info), ctx), ctx.module.asScala.map(visitModule), ctx.id.getText)
+    Circuit(visitInfo(Option(ctx.info), ctx), ctx.module.asScala.map(visitModule).toSeq, ctx.id.getText)
 
   private def visitModule(ctx: ModuleContext): DefModule = {
     val info = visitInfo(Option(ctx.info), ctx)
     ctx.getChild(0).getText match {
-      case "module" => Module(info, ctx.id.getText, ctx.port.asScala.map(visitPort),
+      case "module" => Module(info, ctx.id.getText, ctx.port.asScala.map(visitPort).toSeq,
         if (ctx.moduleBlock() != null)
           visitBlock(ctx.moduleBlock())
         else EmptyStmt)
@@ -96,7 +96,7 @@ class Visitor(infoMode: InfoMode) extends AbstractParseTreeVisitor[FirrtlNode] w
         val defname = if (ctx.defname != null) ctx.defname.id.getText else ctx.id.getText
         val ports = ctx.port.asScala map visitPort
         val params = ctx.parameter.asScala map visitParameter
-        ExtModule(info, ctx.id.getText, ports, defname, params)
+        ExtModule(info, ctx.id.getText, ports.toSeq, defname, params.toSeq)
     }
   }
 
@@ -176,7 +176,7 @@ class Visitor(infoMode: InfoMode) extends AbstractParseTreeVisitor[FirrtlNode] w
           case "Reset" => ResetType
           case "Analog" => if (ctx.getChildCount > 1) AnalogType(getWidth(ctx.intLit(0)))
           else AnalogType(UnknownWidth)
-          case "{" => BundleType(ctx.field.asScala.map(visitField))
+          case "{" => BundleType(ctx.field.asScala.map(visitField).toSeq)
         }
       case typeContext: TypeContext => new VectorType(visitType(ctx.`type`), string2Int(ctx.intLit(0).getText))
     }
@@ -201,10 +201,10 @@ class Visitor(infoMode: InfoMode) extends AbstractParseTreeVisitor[FirrtlNode] w
   }
 
   private def visitBlock(ctx: ModuleBlockContext): Statement =
-    Block(ctx.simple_stmt().asScala.flatMap(x => Option(x.stmt).map(visitStmt)))
+    Block(ctx.simple_stmt().asScala.flatMap(x => Option(x.stmt).map(visitStmt)).toSeq)
 
   private def visitSuite(ctx: SuiteContext): Statement =
-    Block(ctx.simple_stmt().asScala.flatMap(x => Option(x.stmt).map(visitStmt)))
+    Block(ctx.simple_stmt().asScala.flatMap(x => Option(x.stmt).map(visitStmt)).toSeq)
 
   private def visitRuw(ctx: Option[RuwContext]): ReadUnderWrite.Value = ctx match {
     case None => ReadUnderWrite.Undefined
@@ -248,7 +248,7 @@ class Visitor(infoMode: InfoMode) extends AbstractParseTreeVisitor[FirrtlNode] w
 
     // Build map of different Memory fields to their values
     try {
-      parseMemFields(ctx.memField().asScala)
+      parseMemFields(ctx.memField().asScala.toSeq)
     } catch {
       // attach line number
       case e: ParameterRedefinedException => throw new ParameterRedefinedException(s"[$info] ${e.message}")
@@ -268,7 +268,7 @@ class Visitor(infoMode: InfoMode) extends AbstractParseTreeVisitor[FirrtlNode] w
       depth = lit("depth"),
       writeLatency = lit("write-latency").toInt,
       readLatency = lit("read-latency").toInt,
-      readers = readers, writers = writers, readwriters = readwriters,
+      readers = readers.toSeq, writers = writers.toSeq, readwriters = readwriters.toSeq,
       readUnderWrite = ruw
     )
   }
@@ -326,8 +326,8 @@ class Visitor(infoMode: InfoMode) extends AbstractParseTreeVisitor[FirrtlNode] w
         case "node" => DefNode(info, ctx.id(0).getText, visitExp(ctx_exp(0)))
 
         case "stop(" => Stop(info, string2Int(ctx.intLit().getText), visitExp(ctx_exp(0)), visitExp(ctx_exp(1)))
-        case "attach" => Attach(info, ctx_exp map visitExp)
-        case "printf(" => Print(info, visitStringLit(ctx.StringLit), ctx_exp.drop(2).map(visitExp),
+        case "attach" => Attach(info, ctx_exp.map(visitExp).toSeq)
+        case "printf(" => Print(info, visitStringLit(ctx.StringLit), ctx_exp.drop(2).map(visitExp).toSeq,
           visitExp(ctx_exp(0)), visitExp(ctx_exp(1)))
         // formal
         case "assert" => Verification(Formal.Assert, info, visitExp(ctx_exp(0)),
@@ -380,8 +380,8 @@ class Visitor(infoMode: InfoMode) extends AbstractParseTreeVisitor[FirrtlNode] w
         }
       case _: PrimopContext =>
         DoPrim(visitPrimop(ctx.primop),
-               ctx_exp.map(visitExp),
-               ctx.intLit.asScala.map(x => string2BigInt(x.getText)),
+               ctx_exp.map(visitExp).toSeq,
+               ctx.intLit.asScala.map(x => string2BigInt(x.getText)).toSeq,
                UnknownType)
       case _ =>
         ctx.getChild(0).getText match {
diff --git a/src/main/scala/firrtl/analyses/InstanceKeyGraph.scala b/src/main/scala/firrtl/analyses/InstanceKeyGraph.scala
index ab3c9742..49b91788 100644
--- a/src/main/scala/firrtl/analyses/InstanceKeyGraph.scala
+++ b/src/main/scala/firrtl/analyses/InstanceKeyGraph.scala
@@ -81,7 +81,7 @@ object InstanceKeyGraph {
         case other => other.foreachStmt(onStmt)
       }
       onStmt(body)
-      instances
+      instances.toSeq
     }
   }
 
diff --git a/src/main/scala/firrtl/annotations/Target.scala b/src/main/scala/firrtl/annotations/Target.scala
index c89d3120..e7ea07ca 100644
--- a/src/main/scala/firrtl/annotations/Target.scala
+++ b/src/main/scala/firrtl/annotations/Target.scala
@@ -146,7 +146,7 @@ object Target {
         case other =>
       }
     }
-    subComps
+    subComps.toSeq
   }
 
   /** Checks if seq only contains [[TargetToken]]'s with select keywords
diff --git a/src/main/scala/firrtl/annotations/transforms/EliminateTargetPaths.scala b/src/main/scala/firrtl/annotations/transforms/EliminateTargetPaths.scala
index 18d9f449..402f7028 100644
--- a/src/main/scala/firrtl/annotations/transforms/EliminateTargetPaths.scala
+++ b/src/main/scala/firrtl/annotations/transforms/EliminateTargetPaths.scala
@@ -211,7 +211,7 @@ class EliminateTargetPaths extends Transform with DependencyAPIMigration {
     }
 
     // Return modified circuit and associated renameMap
-    (cir.copy(modules = finalModuleList), renameMap, annos)
+    (cir.copy(modules = finalModuleList.toSeq), renameMap, annos)
   }
 
   override def execute(state: CircuitState): CircuitState = {
diff --git a/src/main/scala/firrtl/graph/EulerTour.scala b/src/main/scala/firrtl/graph/EulerTour.scala
index 1e3b02ca..2d8a17e2 100644
--- a/src/main/scala/firrtl/graph/EulerTour.scala
+++ b/src/main/scala/firrtl/graph/EulerTour.scala
@@ -25,7 +25,7 @@ object EulerTour {
     }
 
     tour(start, Vector.empty, 0)
-    new EulerTour(r.toMap, e, h)
+    new EulerTour(r.toMap, e.toSeq, h.toSeq)
   }
 }
 
diff --git a/src/main/scala/firrtl/ir/IR.scala b/src/main/scala/firrtl/ir/IR.scala
index 023f53fd..ad96c18c 100644
--- a/src/main/scala/firrtl/ir/IR.scala
+++ b/src/main/scala/firrtl/ir/IR.scala
@@ -513,7 +513,7 @@ case class Block(stmts: Seq[Statement]) extends Statement {
         its = its.tail
       }
     }
-    Block(res)
+    Block(res.toSeq)
   }
   def mapExpr(f: Expression => Expression): Statement = this
   def mapType(f: Type => Type): Statement = this
diff --git a/src/main/scala/firrtl/options/Shell.scala b/src/main/scala/firrtl/options/Shell.scala
index 28c0554a..88301d30 100644
--- a/src/main/scala/firrtl/options/Shell.scala
+++ b/src/main/scala/firrtl/options/Shell.scala
@@ -29,7 +29,7 @@ class Shell(val applicationName: String) {
       lib.addOptions(parser)
     }
 
-    libraries
+    libraries.toSeq
   }
 
   /** Contains all discovered [[RegisteredTransform]] */
@@ -43,7 +43,7 @@ class Shell(val applicationName: String) {
       tx.addOptions(parser)
     }
 
-    transforms
+    transforms.toSeq
   }
 
   /** The [[AnnotationSeq]] generated from command line arguments
diff --git a/src/main/scala/firrtl/passes/CheckHighForm.scala b/src/main/scala/firrtl/passes/CheckHighForm.scala
index 512602cf..fb5dd1ca 100644
--- a/src/main/scala/firrtl/passes/CheckHighForm.scala
+++ b/src/main/scala/firrtl/passes/CheckHighForm.scala
@@ -96,7 +96,7 @@ trait CheckHighFormLike { this: Pass =>
 
     val intModuleNames = c.modules.view.collect({ case m: Module => m.name }).toSet
 
-    c.modules.view.groupBy(_.name).filter(_._2.length > 1).flatMap(_._2).foreach {
+    c.modules.groupBy(_.name).filter(_._2.length > 1).flatMap(_._2).foreach {
       m => errors.append(new ModuleNameNotUniqueException(m.info, m.name))
     }
 
diff --git a/src/main/scala/firrtl/passes/CheckInitialization.scala b/src/main/scala/firrtl/passes/CheckInitialization.scala
index 1eb16a9b..4a5577f9 100644
--- a/src/main/scala/firrtl/passes/CheckInitialization.scala
+++ b/src/main/scala/firrtl/passes/CheckInitialization.scala
@@ -57,7 +57,7 @@ object CheckInitialization extends Pass {
           case _ => e.foreach(hasVoid)
         }
         hasVoid(e)
-        (void, voidDeps)
+        (void, voidDeps.toSeq)
       }
       def checkInitS(s: Statement): Unit = {
         s match {
diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala
index ab4c9bfa..3c1ff675 100644
--- a/src/main/scala/firrtl/passes/ExpandWhens.scala
+++ b/src/main/scala/firrtl/passes/ExpandWhens.scala
@@ -210,7 +210,7 @@ object ExpandWhens extends Pass {
 
     val attachedAnalogs = attaches.flatMap(_.exprs.map(we)).toSet
     val newBody = Block(Seq(squashEmpty(bodyx)) ++ expandNetlist(netlist, attachedAnalogs) ++
-                            combineAttaches(attaches) ++ simlist)
+                            combineAttaches(attaches.toSeq) ++ simlist)
     Module(m.info, m.name, m.ports, newBody)
   }
 
diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala
index ec674c19..39cb4b9c 100644
--- a/src/main/scala/firrtl/passes/Inline.scala
+++ b/src/main/scala/firrtl/passes/Inline.scala
@@ -106,11 +106,11 @@ class InlineInstances extends Transform with DependencyAPIMigration with Registe
       }
 
       moduleNames.foreach{mn => checkExists(mn.name)}
-      if (errors.nonEmpty) throw new PassExceptions(errors)
+      if (errors.nonEmpty) throw new PassExceptions(errors.toSeq)
       moduleNames.foreach{mn => checkExternal(mn.name)}
-      if (errors.nonEmpty) throw new PassExceptions(errors)
+      if (errors.nonEmpty) throw new PassExceptions(errors.toSeq)
       instanceNames.foreach{cn => checkInstance(cn)}
-      if (errors.nonEmpty) throw new PassExceptions(errors)
+      if (errors.nonEmpty) throw new PassExceptions(errors.toSeq)
    }
 
 
diff --git a/src/main/scala/firrtl/passes/Pass.scala b/src/main/scala/firrtl/passes/Pass.scala
index 4b7a34bf..036bd06a 100644
--- a/src/main/scala/firrtl/passes/Pass.scala
+++ b/src/main/scala/firrtl/passes/Pass.scala
@@ -23,6 +23,6 @@ class Errors {
     case 1 => throw errors.head
     case _ =>
       append(new PassException(s"${errors.length} errors detected!"))
-      throw new PassExceptions(errors)
+      throw new PassExceptions(errors.toSeq)
   }
 }
diff --git a/src/main/scala/firrtl/passes/RemoveAccesses.scala b/src/main/scala/firrtl/passes/RemoveAccesses.scala
index f571bf28..18db5939 100644
--- a/src/main/scala/firrtl/passes/RemoveAccesses.scala
+++ b/src/main/scala/firrtl/passes/RemoveAccesses.scala
@@ -168,7 +168,7 @@ object RemoveAccesses extends Pass {
           case sxx => sxx map fixSource map onStmt
         }
         stmts += sx
-        if (stmts.size != 1) Block(stmts) else stmts(0)
+        if (stmts.size != 1) Block(stmts.toSeq) else stmts(0)
       }
       Module(m.info, m.name, m.ports, squashEmpty(onStmt(m.body)))
     }
diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
index 87a43ce3..cd801570 100644
--- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
+++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
@@ -10,6 +10,8 @@ import firrtl.Utils._
 import firrtl.Mappers._
 import firrtl.options.Dependency
 
+import scala.collection.mutable
+
 case class MPort(name: String, clk: Expression)
 case class MPorts(readers: ArrayBuffer[MPort], writers: ArrayBuffer[MPort], readwriters: ArrayBuffer[MPort])
 case class DataRef(exp: Expression, source: String, sink: String, mask: String, rdwrite: Boolean)
@@ -80,14 +82,14 @@ object RemoveCHIRRTL extends Transform with DependencyAPIMigration {
       types(sx.name) = sx.tpe
       val taddr = UIntType(IntWidth(1 max getUIntWidth(sx.size - 1)))
       val tdata = sx.tpe
-      def set_poison(vec: Seq[MPort]) = vec flatMap (r => Seq(
+      def set_poison(vec: mutable.Seq[MPort]) = vec.toSeq.flatMap (r => Seq(
         IsInvalid(sx.info, SubField(SubField(Reference(sx.name, ut), r.name, ut), "addr", taddr)),
         IsInvalid(sx.info, SubField(SubField(Reference(sx.name, ut), r.name, ut), "clk", ClockType))
       ))
-      def set_enable(vec: Seq[MPort], en: String) = vec map (r =>
+      def set_enable(vec: mutable.Seq[MPort], en: String) = vec.toSeq.map (r =>
         Connect(sx.info, SubField(SubField(Reference(sx.name, ut), r.name, ut), en, BoolType), zero)
       )
-      def set_write(vec: Seq[MPort], data: String, mask: String) = vec flatMap { r =>
+      def set_write(vec: mutable.Seq[MPort], data: String, mask: String) = vec.toSeq.flatMap { r =>
         val tmask = createMask(sx.tpe)
         val portRef = SubField(Reference(sx.name, ut), r.name, ut)
         Seq(IsInvalid(sx.info, SubField(portRef, data, tdata)), IsInvalid(sx.info, SubField(portRef, mask, tmask)))
@@ -105,7 +107,7 @@ object RemoveCHIRRTL extends Transform with DependencyAPIMigration {
         set_enable(rws, "en") ++
         set_write(rws, "wdata", "wmask")
       val mem = DefMemory(sx.info, sx.name, sx.tpe, sx.size, 1, if (sx.seq) 1 else 0,
-                  rds map (_.name), wrs map (_.name), rws map (_.name), sx.readUnderWrite)
+                  rds.map(_.name).toSeq, wrs.map(_.name).toSeq, rws.map(_.name).toSeq, sx.readUnderWrite)
       Block(mem +: stmts)
     case sx: CDefMPort =>
       types.get(sx.mem) match {
@@ -162,8 +164,8 @@ object RemoveCHIRRTL extends Transform with DependencyAPIMigration {
           }
         case MInfer => // do nothing if it's not being used
       }
-      Block(
-        (addrs map (x => Connect(sx.info, SubField(portRef, x, ut), sx.exps.head))) ++
+      Block(List() ++
+        (addrs.map (x => Connect(sx.info, SubField(portRef, x, ut), sx.exps.head))) ++
         (clks map (x => Connect(sx.info, SubField(portRef, x, ut), sx.exps(1)))) ++
         (ens map (x => Connect(sx.info,SubField(portRef, x, ut), one))) ++
          masks.map(lhs => Connect(sx.info, lhs, zero))
@@ -233,7 +235,7 @@ object RemoveCHIRRTL extends Transform with DependencyAPIMigration {
             case Some(wmode) => stmts += Connect(info, wmode, one)
           }
         }
-        if (stmts.isEmpty) sx else Block(sx +: stmts)
+        if (stmts.isEmpty) sx else Block(sx +: stmts.toSeq)
       case PartialConnect(info, loc, expr) =>
         val locx = remove_chirrtl_e(SinkFlow)(loc)
         val rocx = remove_chirrtl_e(SourceFlow)(expr)
@@ -252,7 +254,7 @@ object RemoveCHIRRTL extends Transform with DependencyAPIMigration {
             case Some(wmode) => stmts += Connect(info, wmode, one)
           }
         }
-        if (stmts.isEmpty) sx else Block(sx +: stmts)
+        if (stmts.isEmpty) sx else Block(sx +: stmts.toSeq)
       case sx => sx map remove_chirrtl_s(refs, raddrs) map remove_chirrtl_e(SourceFlow)
     }
   }
diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
index 03c295ed..4847a698 100644
--- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
+++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
@@ -135,7 +135,7 @@ object InferReadWritePass extends Pass {
     (m map inferReadWriteStmt(connects, repl, stmts)
        map replaceStmt(repl)) match {
       case m: ExtModule => m
-      case m: Module => m copy (body = Block(m.body +: stmts))
+      case m: Module => m copy (body = Block(m.body +: stmts.toSeq))
     }
   }
 
diff --git a/src/main/scala/firrtl/passes/memlib/MemConf.scala b/src/main/scala/firrtl/passes/memlib/MemConf.scala
index 4d6ba2c6..5db7de61 100644
--- a/src/main/scala/firrtl/passes/memlib/MemConf.scala
+++ b/src/main/scala/firrtl/passes/memlib/MemConf.scala
@@ -22,7 +22,7 @@ object MemPort {
     s.split(",").toSeq.map(MemPort.apply).map(_ match {
       case Some(x) => x
       case _ => throw new Exception(s"Error parsing MemPort string : ${s}")
-    }).groupBy(identity).mapValues(_.size)
+    }).groupBy(identity).mapValues(_.size).toMap
   }
 }
 
@@ -64,6 +64,6 @@ object MemConf {
       (if (writePorts == 0) Map.empty[MemPort, Int] else Map(MaskedWritePort -> writePorts)) ++
       (if (readWritePorts == 0) Map.empty[MemPort, Int] else Map(MaskedReadWritePort -> readWritePorts))
     }) ++ (if (readPorts == 0) Map.empty[MemPort, Int] else Map(ReadPort -> readPorts))
-    return new MemConf(name, depth, width, ports, maskGranularity)
+    new MemConf(name, depth, width, ports, maskGranularity)
   }
 }
diff --git a/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala b/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala
index 29200631..b5ff10c6 100644
--- a/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala
+++ b/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala
@@ -72,7 +72,7 @@ class ResolveMemoryReference extends Transform with DependencyAPIMigration {
     val noDedups = state.annotations.collect {
       case NoDedupMemAnnotation(ComponentName(cn, ModuleName(mn, _))) => mn -> cn
     }
-    val noDedupMap: Map[String, Set[String]] = noDedups.groupBy(_._1).mapValues(_.map(_._2).toSet)
+    val noDedupMap: Map[String, Set[String]] = noDedups.groupBy(_._1).mapValues(_.map(_._2).toSet).toMap
     state.copy(circuit = run(state.circuit, noDedupMap))
   }
 }
diff --git a/src/main/scala/firrtl/passes/wiring/Wiring.scala b/src/main/scala/firrtl/passes/wiring/Wiring.scala
index 1ee509e2..c62a565e 100644
--- a/src/main/scala/firrtl/passes/wiring/Wiring.scala
+++ b/src/main/scala/firrtl/passes/wiring/Wiring.scala
@@ -196,7 +196,7 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass {
               case Block(sx) => sx
               case s => Seq(s)
             }
-            Module(i, n, ps ++ ports, Block(defines ++ stmts ++ connects))
+            Module(i, n, ps ++ ports, Block(List() ++ defines ++ stmts ++ connects))
           case ExtModule(i, n, ps, dn, p) => ExtModule(i, n, ps ++ ports, dn, p)
         }
     }
diff --git a/src/main/scala/firrtl/proto/FromProto.scala b/src/main/scala/firrtl/proto/FromProto.scala
index 891dc2ba..dced9c2d 100644
--- a/src/main/scala/firrtl/proto/FromProto.scala
+++ b/src/main/scala/firrtl/proto/FromProto.scala
@@ -8,7 +8,9 @@ import java.io.{File, FileInputStream, InputStream}
 import collection.JavaConverters._
 import FirrtlProtos._
 import com.google.protobuf.CodedInputStream
-import Firrtl.Statement.{ReadUnderWrite, Formal}
+import Firrtl.Statement.{Formal, ReadUnderWrite}
+
+import scala.collection.mutable
 
 object FromProto {
 
@@ -34,10 +36,10 @@ object FromProto {
   }
 
   // Convert from ProtoBuf message repeated Statements to FIRRRTL Block
-  private def compressStmts(stmts: Seq[ir.Statement]): ir.Statement = stmts match {
-    case Seq() => ir.EmptyStmt
-    case Seq(stmt) => stmt
-    case multiple => ir.Block(multiple)
+  private def compressStmts(stmts: mutable.Seq[ir.Statement]): ir.Statement = stmts match {
+    case mutable.Seq() => ir.EmptyStmt
+    case mutable.Seq(stmt) => stmt
+    case multiple => ir.Block(multiple.toSeq)
   }
 
   def convert(info: Firrtl.SourceInfo): ir.Info =
@@ -86,8 +88,8 @@ object FromProto {
     ir.SubAccess(convert(access.getExpression), convert(access.getIndex), ir.UnknownType)
 
   def convert(primop: Firrtl.Expression.PrimOp): ir.DoPrim = {
-    val args = primop.getArgList.asScala.map(convert(_))
-    val consts = primop.getConstList.asScala.map(convert(_))
+    val args = primop.getArgList.asScala.map(convert(_)).toSeq
+    val consts = primop.getConstList.asScala.map(convert(_)).toSeq
     ir.DoPrim(convert(primop.getOp), args, consts, ir.UnknownType)
   }
 
@@ -173,7 +175,7 @@ object FromProto {
   }
 
   def convert(printf: Firrtl.Statement.Printf, info: Firrtl.SourceInfo): ir.Print = {
-    val args = printf.getArgList.asScala.map(convert(_))
+    val args = printf.getArgList.asScala.map(convert(_)).toSeq
     val str = ir.StringLit(printf.getValue)
     ir.Print(convert(info), str, args, convert(printf.getClk), convert(printf.getEn))
   }
@@ -193,9 +195,9 @@ object FromProto {
 
   def convert(mem: Firrtl.Statement.Memory, info: Firrtl.SourceInfo): ir.DefMemory = {
     val dtype = convert(mem.getType)
-    val rs = mem.getReaderIdList.asScala
-    val ws = mem.getWriterIdList.asScala
-    val rws = mem.getReadwriterIdList.asScala
+    val rs = mem.getReaderIdList.asScala.toSeq
+    val ws = mem.getWriterIdList.asScala.toSeq
+    val rws = mem.getReadwriterIdList.asScala.toSeq
     import Firrtl.Statement.Memory._
     val depth = mem.getDepthCase.getNumber match {
       case UINT_DEPTH_FIELD_NUMBER => BigInt(mem.getUintDepth)
@@ -206,7 +208,7 @@ object FromProto {
   }
 
   def convert(attach: Firrtl.Statement.Attach, info: Firrtl.SourceInfo): ir.Attach = {
-    val exprs = attach.getExpressionList.asScala.map(convert(_))
+    val exprs = attach.getExpressionList.asScala.map(convert(_)).toSeq
     ir.Attach(convert(info), exprs)
   }
 
@@ -280,7 +282,7 @@ object FromProto {
       case RESET_TYPE_FIELD_NUMBER => ir.ResetType
       case ANALOG_TYPE_FIELD_NUMBER => convert(tpe.getAnalogType)
       case BUNDLE_TYPE_FIELD_NUMBER =>
-        ir.BundleType(tpe.getBundleType.getFieldList.asScala.map(convert(_)))
+        ir.BundleType(tpe.getBundleType.getFieldList.asScala.map(convert(_)).toSeq)
       case VECTOR_TYPE_FIELD_NUMBER => convert(tpe.getVectorType)
     }
   }
@@ -311,16 +313,16 @@ object FromProto {
 
   def convert(module: Firrtl.Module.UserModule): ir.Module = {
     val name = module.getId
-    val ports = module.getPortList.asScala.map(convert(_))
-    val stmts = module.getStatementList.asScala.map(convert(_))
+    val ports = module.getPortList.asScala.map(convert(_)).toSeq
+    val stmts = module.getStatementList.asScala.map(convert(_)).toSeq
     ir.Module(ir.NoInfo, name, ports, ir.Block(stmts))
   }
 
   def convert(module: Firrtl.Module.ExternalModule): ir.ExtModule = {
     val name = module.getId
-    val ports = module.getPortList.asScala.map(convert(_))
+    val ports = module.getPortList.asScala.map(convert(_)).toSeq
     val defname = module.getDefinedName
-    val params = module.getParameterList.asScala.map(convert(_))
+    val params = module.getParameterList.asScala.map(convert(_)).toSeq
     ir.ExtModule(ir.NoInfo, name, ports, defname, params)
   }
 
@@ -335,7 +337,7 @@ object FromProto {
     require(proto.getCircuitCount == 1, "Only 1 circuit is currently supported")
     val c = proto.getCircuit(0)
     require(c.getTopCount == 1, "Only 1 top is currently supported")
-    val modules = c.getModuleList.asScala.map(convert(_))
+    val modules = c.getModuleList.asScala.map(convert(_)).toSeq
     val top = c.getTop(0).getName
     ir.Circuit(ir.NoInfo, modules, top)
   }
diff --git a/src/main/scala/firrtl/stage/phases/Compiler.scala b/src/main/scala/firrtl/stage/phases/Compiler.scala
index 66dad55e..e3a96b0e 100644
--- a/src/main/scala/firrtl/stage/phases/Compiler.scala
+++ b/src/main/scala/firrtl/stage/phases/Compiler.scala
@@ -82,7 +82,7 @@ class Compiler extends Phase with Translator[AnnotationSeq, Seq[CompilerRun]] {
         case annotation => d.copy(annotations = annotation +: d.annotations)
       }
     }
-    c
+    c.toSeq
   }
 
   /** Expand compiler output back into an [[AnnotationSeq]]. Annotations used in the construction of the compiler run are
diff --git a/src/main/scala/firrtl/transforms/ConstantPropagation.scala b/src/main/scala/firrtl/transforms/ConstantPropagation.scala
index 0ec4fe0b..c3c615e0 100644
--- a/src/main/scala/firrtl/transforms/ConstantPropagation.scala
+++ b/src/main/scala/firrtl/transforms/ConstantPropagation.scala
@@ -819,7 +819,7 @@ class ConstantPropagation extends Transform with DependencyAPIMigration with Res
     }
     // Map from module name to component names
     val dontTouchMap: Map[OfModule, Set[String]] =
-      dontTouches.groupBy(_._1).mapValues(_.map(_._2).toSet)
+      dontTouches.groupBy(_._1).mapValues(_.map(_._2).toSet).toMap
 
     state.copy(circuit = run(state.circuit, dontTouchMap))
   }
diff --git a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala
index 4182e496..f9e35818 100644
--- a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala
+++ b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala
@@ -94,7 +94,7 @@ class DeadCodeElimination extends Transform
       e
     }
     rec(expr)
-    refs
+    refs.toSeq
   }
 
   // Gets all dependencies and constructs LogicNodes from them
diff --git a/src/main/scala/firrtl/transforms/Dedup.scala b/src/main/scala/firrtl/transforms/Dedup.scala
index 03b5faa9..30558129 100644
--- a/src/main/scala/firrtl/transforms/Dedup.scala
+++ b/src/main/scala/firrtl/transforms/Dedup.scala
@@ -550,7 +550,7 @@ object DedupModules extends LazyLogging {
     }
 
     changeInternals(rename, retype, {i => i}, {(x, y) => x}, renameExps = false)(m)
-    refs
+    refs.toIndexedSeq
   }
 
   def computeRenameMap(originalNames: IndexedSeq[ReferenceTarget],
@@ -578,6 +578,6 @@ object DedupModules extends LazyLogging {
     }
 
     onExp(root)
-    all
+    all.toSeq
   }
 }
diff --git a/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala b/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala
index 4bda25ce..b272f134 100644
--- a/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala
+++ b/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala
@@ -107,7 +107,7 @@ object FlattenRegUpdate {
     }
 
     val bodyx = onStmt(mod.body)
-    mod.copy(body = Block(bodyx +: regUpdates))
+    mod.copy(body = Block(bodyx +: regUpdates.toSeq))
   }
 
 }
diff --git a/src/main/scala/firrtl/transforms/GroupComponents.scala b/src/main/scala/firrtl/transforms/GroupComponents.scala
index 3b982fbf..166feba0 100644
--- a/src/main/scala/firrtl/transforms/GroupComponents.scala
+++ b/src/main/scala/firrtl/transforms/GroupComponents.scala
@@ -261,13 +261,13 @@ class GroupComponents extends Transform with DependencyAPIMigration {
           val topStmts = mutable.ArrayBuffer[Statement]()
           val group = byNode(r.name)
           groupStatements(group) += r mapExpr inGroupFixExps(group, topStmts)
-          Block(topStmts)
+          Block(topStmts.toSeq)
         case c: Connect if byNode(getWRef(c.loc).name) != "" =>
           // Sink is in a group
           val topStmts = mutable.ArrayBuffer[Statement]()
           val group = byNode(getWRef(c.loc).name)
           groupStatements(group) += Connect(c.info, c.loc, inGroupFixExps(group, topStmts)(c.expr))
-          Block(topStmts)
+          Block(topStmts.toSeq)
         case i: IsInvalid if byNode(getWRef(i.expr).name) != "" =>
           // Sink is in group
           val group = byNode(getWRef(i.expr).name)
@@ -289,7 +289,7 @@ class GroupComponents extends Transform with DependencyAPIMigration {
 
     // For all group labels (not including the original module label), return a new Module.
     val newModules = labelOrder.filter(_ != "") map { group =>
-      Module(NoInfo, label2module(group), groupPorts(group).distinct, Block(groupStatements(group).distinct))
+      Module(NoInfo, label2module(group), groupPorts(group).distinct.toSeq, Block(groupStatements(group).distinct.toSeq))
     }
     Seq(m.copy(body = finalTopBody)) ++ newModules
   }
diff --git a/src/main/scala/firrtl/transforms/InferResets.scala b/src/main/scala/firrtl/transforms/InferResets.scala
index 1798e3d8..ebf1d67a 100644
--- a/src/main/scala/firrtl/transforms/InferResets.scala
+++ b/src/main/scala/firrtl/transforms/InferResets.scala
@@ -90,7 +90,7 @@ object InferResets {
           tokens.groupBy { case (TargetToken.Field(n) +: t, _) => n }
                 .mapValues { ts =>
                   fromTokens(ts.map { case (_ +: t, tpe) => (t, tpe) }:_*)
-                }
+                }.toMap
         BundleTree(fields)
     }
   }
@@ -281,7 +281,7 @@ class InferResets extends Transform with DependencyAPIMigration {
   private def makeDeclMap(map: Map[ReferenceTarget, Type]): Map[String, TypeTree] =
     map.groupBy(_._1.ref).mapValues { ts =>
       TypeTree.fromTokens(ts.toSeq.map { case (target, tpe) => (target.component, tpe) }:_*)
-    }
+    }.toMap
 
   private def implPort(map: Map[String, TypeTree])(port: Port): Port =
     map.get(port.name)
diff --git a/src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala b/src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala
index 6bc948cd..4ed50046 100644
--- a/src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala
+++ b/src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala
@@ -80,7 +80,9 @@ class PropagatePresetAnnotations extends Transform with DependencyAPIMigration {
     // store async-reset trees
     val asyncCoMap = new TargetSetMap()
     // Annotations to be appended and returned as result of the transform
-    val annos = cs.annotations.to[mutable.ArrayBuffer] -- presetAnnos
+    val annos = (cs.annotations.toSet -- presetAnnos).to(mutable.ArrayBuffer)
+    // TODO: annotations should be filtered with a .partition instead of trying to do set operations
+    //       to filter out the non-preset annotations
 
     val circuitTarget = CircuitTarget(cs.circuit.main)
 
@@ -301,7 +303,7 @@ class PropagatePresetAnnotations extends Transform with DependencyAPIMigration {
 
     cs.circuit.foreachModule(processModule) // PHASE 1 : Initialize
     annotateAsyncSet(asyncToAnnotate)       // PHASE 2 : Annotate
-    annos
+    annos.toSeq
   }
 
   /*
diff --git a/src/main/scala/firrtl/transforms/RemoveWires.scala b/src/main/scala/firrtl/transforms/RemoveWires.scala
index 0e70ec1f..f692e513 100644
--- a/src/main/scala/firrtl/transforms/RemoveWires.scala
+++ b/src/main/scala/firrtl/transforms/RemoveWires.scala
@@ -51,7 +51,7 @@ class RemoveWires extends Transform with DependencyAPIMigration {
       e
     }
     rec(expr)
-    refs
+    refs.toSeq
   }
 
   // Transform netlist into DefNodes
@@ -142,7 +142,7 @@ class RemoveWires extends Transform with DependencyAPIMigration {
         onStmt(body)
         getOrderedNodes(netlist, regInfo) match {
           case Success(logic) =>
-            Module(info, name, ports, Block(decls ++ logic ++ otherStmts))
+            Module(info, name, ports, Block(List() ++ decls ++ logic ++ otherStmts))
           // If we hit a CyclicException, just abort removing wires
           case Failure(c: CyclicException) =>
             val problematicNode = c.node