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AgeCommit message (Expand)Author
2021-07-25Add typedef in DependencyManager.Jiuyang Liu
2021-07-14Fix memory annotation deduplication (#2286)Jared Barocsi
2021-07-11Rm java.io in WriteEmitted (#2275)sinofp
2021-07-11Deprecate BlackBoxResourceAnno (#2262)Schuyler Eldridge
2021-07-07Replace hard coded line separators with system specific ones (#2281)Boyang Han
2021-06-25Correct a typo in src/main/scala/firrtl/WIR.scala (#2283)Felix Yan
2021-06-22Fix VerilogMemDelays use before declaration (#2278)Jack Koenig
2021-06-18Fix MultiInfo parser + serialization bug (#2265)Jared Barocsi
2021-06-17smt: include firrtl statement names in SMT and btor2 output (#2270)Kevin Laeufer
2021-06-17Add --start-from option (#2273)Schuyler Eldridge
2021-06-17Add Protocol Buffer emission (#2271)Schuyler Eldridge
2021-06-15make PresetRegAnnotation public (#2254)Kevin Laeufer
2021-06-14Add -X mhigh compiler for minimal high form (#2268)Schuyler Eldridge
2021-06-08Prepend target dir to default dedup report dirsinofp
2021-06-08Rm java.io in MustDedupsinofp
2021-06-05Add deprecation annotation in FileUtilssinofp
2021-06-04Rm java.io in FileUtilssinofp
2021-06-03Replace mem macros renaming (#2243)Albert Chen
2021-05-22Rewrite vlsi_mem_gen into a Firrtl Transform (#2202)sinofp
2021-05-21Optimize Annotation.getTargets (#2244)Jack Koenig
2021-05-21Fix renaming of local targets in InlineInstances (#2238)Albert Chen
2021-05-21Annotation: override getTargets for SingleTargetAnnotation (#2241)Kevin Laeufer
2021-05-21WiringTransform: cannot run after RemoveWires (#2240)Kevin Laeufer
2021-05-18Improve performance of RenameMap in LowerTypes (#2233)Jack Koenig
2021-05-17Use os-lib to rewrite Z3ModelChecker (#2223)Jiuyang Liu
2021-05-14Add JsonProtocol.serializeRecover (#2227)Jack Koenig
2021-05-13Implement MFC-style source locator compression (#2212)Jared Barocsi
2021-05-04Make MustDeduplicateAnnotation deletable (#2215)Jack Koenig
2021-04-27Memlib Refactor (#2191)Jiuyang Liu
2021-04-27deprecate memlib APIs modifided in #2191. (#2199)Jiuyang Liu
2021-04-22Fix CheckWidths error message for uninferred width (#2196)Fabian Schuiki
2021-04-19Hoist Transform timing to the Phase level (#2190)Jack Koenig
2021-04-19Don't use declaration-assigns for wires representing mem ports (#2189)Albert Magyar
2021-04-16Make InferTypes error on enable conditions > 1-bit wide (#2182)Jack Koenig
2021-04-16Fix signedness of xor const prop with zero (#2179)Fabian Schuiki
2021-04-13Add indent parameter to Serializer.serialize() (#2177)Jared Barocsi
2021-04-11smt: use existing bitWidth API (#2175)edwardcwang
2021-04-06Deprecate InlineCasts, add InlineAcrossCasts (#2146)Jack Koenig
2021-04-05Establish a fixed relative order for FPGA-backed passes + reflect in ScalaDocAlbert Magyar
2021-04-05Add test for SeparateWriteClocksAlbert Magyar
2021-04-05Add --target:fpga flag to prioritize FPGA-friendly compilationAlbert Magyar
2021-04-05Add SeparateWriteClocks to ensure one mem write per Verilog processAlbert Magyar
2021-04-05Add tests for same-address readwrite inferenceAlbert Magyar
2021-04-05Allow InferReadWrite to combine shared-address R/W ports when appropriateAlbert Magyar
2021-04-05Add SetDefaultReadUnderWrite transformAlbert Magyar
2021-04-05Optionally allow simple SyncReadMems to pass through VerilogMemDelaysAlbert Magyar
2021-04-05Allow direct emission of sync-read memories to VerilogAlbert Magyar
2021-04-05Specify that SimplifyMems invalidates InferTypesAlbert Magyar
2021-04-01Add memory initialization options for synthesis (#2166)Carlos Eduardo
2021-03-29Fix RemoveAccesses, delete CSESubAccesses (#2157)Jack Koenig
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