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AgeCommit message (Expand)Author
2015-05-19mergejackbackrack
2015-05-19get flo backend running again with no pads and generic operatorsjackbackrack
2015-05-19Added support for non-inlined modules in verilog backendazidar
2015-05-18get coercion running for flo backend and disable negative lit checkjackbackrack
2015-05-18First pass at a Verilog Backend. Not tested, but compiles and generates reaso...azidar
2015-05-18Big API Change. Pad is no longer supported. Widths of primops can be flexible...azidar
2015-05-15Updated firrtl for its passes to be a bit more modular, and to enable pluggin...azidar
2015-05-14mergejackbackrack
2015-05-13Added source indicators from FIRRTL files. Pass in -p i to get them printed. ...azidar
2015-05-13Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bugazidar
2015-05-07do signed padding as welljackbackrack
2015-05-05Added a bunch of tests. In the middle of implementing check kinds and check t...azidar
2015-05-04mergejackbackrack
2015-05-04Added new stanzaazidar
2015-05-04Fixed bug where instance types were not loweredazidar
2015-05-04mergejackbackrack
2015-05-04Merge branch 'master' of github.com:ucb-bar/firrtlazidar
2015-05-04Updated stuffazidar
2015-05-04add reduction operatorsjackbackrack
2015-05-04Merge pull request #6 from jackbackrack/masterAdam Izraelevitz
2015-05-04Added a few more error checks. Not tested yet. Fixed bug in pad type inferenceazidar
2015-05-04mergejackbackrack
2015-05-04Fixed change where type of mux-ss was incorrectazidar
2015-05-02mergejackbackrack
2015-05-02Added a infrastructure for check passes, and wrote a fewazidar
2015-05-02Now when expanding ConnectFrom/ToIndex, create a node for the index so it isn...azidar
2015-05-01add arsh refsjackbackrack
2015-05-01Bug fix. ExpWidth was improperly evaluated during simplify (not subtracting one)azidar
2015-05-01Fixed performance bug where PlusWidth, MinusWidth, and ExpWidth could be simp...azidar
2015-05-01mergejackbackrack
2015-05-01adjust sizeof to be correctjackbackrack
2015-05-01Fixed bug where the enable was looked at for lowering MUX.azidar
2015-04-30mergejackbackrack
2015-04-30Fixed assignment to outputs not getting emitted from Expand When passazidar
2015-04-30mergejackbackrack
2015-04-30turn off printingjackbackrack
2015-04-30Fixed bug that added multiple arguements to OR, instead of a reduce-orazidar
2015-04-29mergejackbackrack
2015-04-29mergejackbackrack
2015-04-29add dyn shifts to flo backendjackbackrack
2015-04-29Fixed bug where a node's width was not equal to its value'sazidar
2015-04-29Made temp name generation counter, as well as the name, based off the eventua...azidar
2015-04-29Fixed bug in lowering of subfields. Fixed ModuleVec.fir to be correctazidar
2015-04-29mergejackbackrack
2015-04-29turn off printingjackbackrack
2015-04-29Added dshl and dshrazidar
2015-04-28mergejackbackrack
2015-04-28Instances are now male. Reworked lowering pass to be sane. chisel3/ModuleVec....azidar
2015-04-27mergejackbackrack
2015-04-27fix ops to get tests passing through flo-llvmjackbackrack
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