aboutsummaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorazidar2015-04-29 19:23:03 -0700
committerazidar2015-04-29 19:23:03 -0700
commit0608bfbe363780132c0baf1e7098013ab4352f34 (patch)
tree9924e424c3a3a0f7644720f4bf19a900c3b8c83d /src
parent7c0d0af5b91fcdc2a0cf9619b76be5529968487d (diff)
Fixed bug where a node's width was not equal to its value's
Diffstat (limited to 'src')
-rw-r--r--src/main/stanza/passes.stanza7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 39795a62..5d2abb81 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -1520,7 +1520,12 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod
(s:DefWire) : DefWire(name(s),h[name(s)])
(s:DefInstance) : DefInstance(name(s),gen-constraints(module(s)))
(s:DefMemory) : DefMemory(name(s),h[name(s)] as VectorType)
- (s:DefNode) : DefNode(name(s),gen-constraints(value(s)))
+ (s:DefNode) :
+ val l = h[name(s)]
+ val r = gen-constraints(value(s))
+ add(v,WGeq(width!(l),width!(type(r))))
+ add(v,WGeq(width!(type(r)),width!(l)))
+ DefNode(name(s),r)
(s:Connect) :
val l = gen-constraints(loc(s))
val e = gen-constraints(exp(s))