aboutsummaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Expand)Author
2020-11-16make LazyLogging log to console by default. (#1961)Jiuyang Liu
2020-11-12Fix RemoveWires handling of invalidated non-UInt wires (#1949)Jack Koenig
2020-11-11smt: add support for write-first memories (#1948)Kevin Laeufer
2020-11-10Fix SMT Memory Bug (#1942)Kevin Laeufer
2020-11-10Refactor emiter (#1879)Jiuyang Liu
2020-11-09smt: ensure that all signals have a unique name (#1943)Kevin Laeufer
2020-11-07-full64 is required to detect VCS. (#1930)Jiuyang Liu
2020-11-04Remove caching from RenameMap (#1938)Jack Koenig
2020-10-26fix for LoweringCompilersSpec.Jiuyang liu
2020-10-26bug fix for VerilogPrep using wrong type.Jiuyang liu
2020-10-26fix a test not detecting verilog name conflicts.Jiuyang liu
2020-10-13Make {Stage, FirrtlStage}.run protected (#1926)Schuyler Eldridge
2020-10-01Fix "fix" for negative literals > 32 bitsJack Koenig
2020-09-30Add test for chaining RW-port rdata as wdata of another memAlbert Magyar
2020-09-30Handle case where rdata of mem RW port split to R+W ports drives another memAlbert Magyar
2020-09-30Speed up writing CustomFileEmission with buffering (#1906)Jack Koenig
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-09-15Don't use ResolvedAnnotationPaths in ConstProp nor DCE (#1896)Jack Koenig
2020-09-14Hit connect case in DedupModuleTests (#1716)Schuyler Eldridge
2020-09-09Make StageOption Unserializable (#1891)Jack Koenig
2020-09-09Loosen inlining restrictions (#1882)Albert Chen
2020-09-06Add --pretty:no-expr-inlining to prevent expression inlining (#1869)Jack Koenig
2020-09-06Support binary files in CustomFileEmission (#1887)Jack Koenig
2020-09-05Better error messages for unserializable annotations (#1885)Jack Koenig
2020-09-04Add test for mem port clock legalizationAlbert Magyar
2020-09-04Legalize memory port clocksAlbert Magyar
2020-09-01InlineBooleanExpressions: test DontTouch (#1880)Albert Chen
2020-08-31Emitter: add missing parenthesize calls (#1874)Albert Chen
2020-08-28Add test for InlineBooleanExpressions add-not exampleAlbert Magyar
2020-08-28Restrict boolean inlining to avoid context-sensitive width bugsAlbert Magyar
2020-08-28Add custom transforms 'upstream' of emitter annotation in equiv testsAlbert Magyar
2020-08-28FlattenSpec: flattening a module with no instaces should be a no-op (#1868)Kevin Laeufer
2020-08-28Deprecate CompilerAnnotation (#1870)Schuyler Eldridge
2020-08-26smt: ignore clock signals when converting to transition system (#1866)Kevin Laeufer
2020-08-26Scalafmt check all (#1867)Kevin Laeufer
2020-08-26Emit parentheses in Verilog for nested unary ops (#1865)Jack Koenig
2020-08-25Inline Boolean Expressions (#1817)Albert Chen
2020-08-24Make ir.Serializer support custom FirrtlNodes (#1857)Jack Koenig
2020-08-22Async reset tieoff bug (#1854)David Biancolin
2020-08-21Deprecate Uniquify and move its useful utilities (#1856)Jack Koenig
2020-08-21Fix Uniquify bug and improve ReplaceSeqMems transforms (#1855)Jack Koenig
2020-08-14Apply scalafmt againJack Koenig
2020-08-14All of src/ formatted with scalafmtchick
2020-08-14Tell Scalafmt to ignore large literal collectionsJack Koenig
2020-08-15experimental SMTLib and btor2 emitter (#1826)Kevin Laeufer
2020-08-14tests: Decrease Dependency on Deprecated APIs (#1839)Kevin Laeufer
2020-08-13Deprecate support for Scala 2.11 (#1842)Jack Koenig
2020-08-13Remove LegacyAnnotation and [most] MoultingYaml (#1833)Jack Koenig
2020-08-13Cleanup Named Targets (#1311)Schuyler Eldridge
2020-08-12Combined Uniquify and LowerTypes pass (#1784)Kevin Laeufer
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 14:10:20 +0000