| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-04-21 | Fix optimization of register with reset but invalid connection (#2520) | Jack Koenig | |
| Fixes #2516 Previously, reg r : UInt<8>, clock with : reset => (p, UInt<8>(3)) r is invalid would compile to: reg r : UInt<8>, clock r <= UInt<8>(0) now it compiles to: reg r : UInt<8>, clock wire r_1 : UInt<8> r_1 is invalid r <= mux(reset, UInt<8>(3), r_1) This is consistent with the behavior for a reset with an asynchronous reset. | |||
| 2020-09-16 | Change to Apache 2.0 License (#1901) | Chick Markley | |
| 2020-08-14 | All of src/ formatted with scalafmt | chick | |
| 2020-05-18 | Canonicalize init of regs with zero as reset in RemoveReset (#1627) | Albert Magyar | |
| * Fixes #1561 * Add test for zero-reset reg from #1561 | |||
| 2020-03-17 | [RFC] Factor out common test classes; package them (#1412) | David Biancolin | |
| * Pull out common test utilities into a separate package * Project a fat jar for test utilities Co-authored-by: Albert Magyar <albert.magyar@gmail.com> | |||
| 2019-08-07 | Add tests on RemoveReset of invalid inits | Schuyler Eldridge | |
| Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> | |||
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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