sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2021-09-23	transforms.formal: ensure named statements as output (#2367)	Kevin Laeufer

2020-09-16	Change to Apache 2.0 License (#1901)	Chick Markley

2020-08-14	All of src/ formatted with scalafmt	chick

2020-08-07	ExpandWhens: VerificationStatements should be part of the simlist (#1829)	Kevin Laeufer

2020-07-08	ir: add faster serializer (#1694)	Kevin Laeufer
	This Serializer which is implemented external to the IR node definition uses a StringBuilder to achieve about a 1.7x performance improvement when serializing. Eventually, all implementations of the `serialize` methd should be replaced with a call to `Serializer.serialize`. However, for this PR we keep the old code in place in order to allow for easy regression testing with the benchmark JAR like this: > java -cp utils/bin/firrtl-benchmark.jar \ firrtl.benchmark.hot.SerializationBenchmark \ ~/benchmarks/medium.pb 2 5 test Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-07	verification: emit mesage as Verilog comment (#1712)	Kevin Laeufer
	Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-06-26	Add test for ConvertAsserts	Albert Magyar
	* Add testcase for empty message
2020-06-23	Basic model checking API (#1653)	Tom Alcorn
	* Add assume, assert, cover statements * Assert submodule assumptions * Add warning when removing verification statements * Remove System Verilog behaviour emitter warning * Add option to disable AssertSubmoduleAssumptions * Document verification statements in the spec The syntax for the new statements is assert(clk, cond, en, msg) assume(clk, cond, en, msg) cover(clk, cond, en, msg) With assert as a representative example, the semantics is as follows: `clk` is the clock, `cond` is the expression being asserted, `en` is the enable signal (if `en` is low then the assert is not checked) and `msg` is a string message intended to be reported as an error message by the model checker if the assertion fails. In the Verilog emitter, the new statements are handled by a new `formals` map, which groups the statements by clock domain. All model checking statements are then emitted within the context of an `ifdef FORMAL` block, which allows model checking tools (like Symbiyosys) to utilize the statements while keeping them out of synthesis flows. Co-authored-by: Albert Magyar <albert.magyar@gmail.com>