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* allow for zero-width integer literals
* CheckWidths: ensure that width is non-negative
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* Fix dshl zero-width shift behavior
Add a special case for dshl handling in the ZeroWidths pass. If one
expression is shifted by a second, zero-width expression, just return
the first expression. This prevents a bug where the width will
incorrectly expand due to zero-widths introducing a 1-bit zero
expression.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* fixup! Fix dshl zero-width shift behavior
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* Fix bug in zero-width memory removal
Correctly remove all extraneous connections to all types of memory
ports (read, write, readwrite) for zero-width memories. Previously,
only read ports were correctly handled.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* fixup! Fix bug in zero-width memory removal
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Previously, concatenating two SInts where one is of zero-width would
return the non-zero-width SInt. This is incorrect because the output of
Cat should be of type UInt. Now the ZeroWidth transform will introduce a
cast when removing a Cat when the argument type is non-UInt.
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* Pull out common test utilities into a separate package
* Project a fat jar for test utilities
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Fixes #1344
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Major features:
- Added Interval type, as well as PrimOps asInterval, clip, wrap, and sqz.
- Changed PrimOp names: bpset -> setp, bpshl -> incp, bpshr -> decp
- Refactored width/bound inferencer into a separate constraint solver
- Added transforms to infer, trim, and remove interval bounds
- Tests for said features
Plan to be released with 1.3
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The following names are changed:
- gender -> flow
- Gender -> Flow
- MALE -> SourceFlow
- FEMALE -> SinkFlow
- BIGENDER -> DuplexFlow
- UNKNOWNGENDER -> UnknownFlow
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* refactor InferWidths to allow for extra contraints, add InferWidthsWithAnnos
* add test cases
* add ResolvedAnnotationPaths trait to InferWidthsWithAnnos
* remove println
* cleanup tests
* remove extraneous constraints
* use foreachStmt instead of mapStmt
* remove support for aggregates
* fold InferWidthsWithAnnos into InferWidths
* throw exception if ref not found, check for annos before AST walk
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This should close #757. It should also allow for stop() and printf()
to be used with zero-width fields.
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* Added pass name to debug logger
* Addresses #459. Rewords transform annotations API.
Now, any annotation not propagated by a transform is considered deleted.
A new DeletedAnnotation is added in place of it.
* Added more stylized debugging style
* WIP: make pass transform
* WIP: All tests pass, need to pull master
* Cleaned up PR
* Added rename updates to all core transforms
* Added more rename tests, and bugfixes
* Renaming tracks non-leaf subfields
E.g. given:
wire x: {a: UInt<1>, b: UInt<1>[2]}
Annotating x.b will eventually annotate x_b_0 and x_b_1
* Bugfix instance rename lowering broken
* Address review comments
* Remove check for seqTransform, UnknownForm too restrictive check
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Now remove DefNodes of zero width
Don't deeply walk nodes (was the source of the bug)
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* Added Zero width wires.
Semantics:
- No change to width inference rules, e.g.
a<0> + b<2> = c<3>
- Replace zero width wires with UInt<1>(0) or SInt<1>(0)
- Performs constant prop.
- Redo width/type inference
* Remove errant println
* Moved ZeroWidth after ConvertFixedToSInt
* Added more tests, bugfix match on connect
Also replaced constprop with infertypes for correctness
* Updated to new emitter and test infrastructure
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