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* Pull out common test utilities into a separate package
* Project a fat jar for test utilities
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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The following names are changed:
- gender -> flow
- Gender -> Flow
- MALE -> SourceFlow
- FEMALE -> SinkFlow
- BIGENDER -> DuplexFlow
- UNKNOWNGENDER -> UnknownFlow
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* refactor InferWidths to allow for extra contraints, add InferWidthsWithAnnos
* add test cases
* add ResolvedAnnotationPaths trait to InferWidthsWithAnnos
* remove println
* cleanup tests
* remove extraneous constraints
* use foreachStmt instead of mapStmt
* remove support for aggregates
* fold InferWidthsWithAnnos into InferWidths
* throw exception if ref not found, check for annos before AST walk
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This changes the CheckTypes.UniferredWidth exception to include the pretty
printed Target that was uninferred and suggests to the user that they may
have forgotten to assign to it. This changes the CheckTypes pass to
communicate the necessary Target information during AST traversal such
that when an uninferred width is found, the Target is known and available.
This also adds one test checking the message of the UniferredWidth
exception.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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It is O(n) and every use is in an O(n) iteration resulting in O(n^2).
Same information can be extracted from create_exps which happens to also
be called at every use of get_flip.
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Also minor cleanup to literal construction in Visitor
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* Changed primops to not accept mixed-type args
* Changed return type of sub of two uints to uint
* Added negative tests
* Removed rocket.fir. Manually changed RocketCore to not mix mul arg types. Added integration tests
* Clarified test description and remove println
* Fixed use of throwInternalError
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Also base max dshl check on MaxWidth instead of just 31 bits
Resolves #320
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This will certainly lead to more uninferred width errors, but now widths
that were previously incorrectly inferred are now correctly uninferred.
An example is:
reg r : UInt, clock with: (reset => (reset, UInt<2>(3)))
node x = add(r, r)
r <= x
Here, r's width follows the following formula, which cannot be solved:
rWidth >= max(max(rWidth, rWidth) + 1, 2)
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Replace with more sensible comment to see LICENSE rather than including the
whole license in every file
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* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers
* Transforms define inputForm and outputForm
* Custom transforms can be inserted at runtime into compiler or the Driver
* Current "built-in" custom transforms handled via above mechanism
* Verilog-specific passes moved to the Verilog emitter
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Address #297
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Fixes #308
Fixes #193
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