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Transformation of mem readwriters whose address contain references to
readwriters of mems declared before it would contain invalid references
to untransformed memory readwriter, as the connection is not transformed.
This commit fixes this issue.
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* rearrange passes to enable optimized firrtl emission
* Support ConstProp on padded arguments to comparisons with literals
* Move shr legalization logic into ConstProp
Continue calling ConstProp of shr in Legalize.
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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The pass injects pipe registers immediately after the declaration of the
memory. This can be problematic if the clock for the associated memory
port is defined after the declaration of the memory. For any memory port
clocks that are driven by non-ports, we now inject a wire before the
pipe register declarations to be sure there are no
use-before-declaration issues.
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* Also clean up VerilogMemDelaySpec structure
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* Removed unused imports in src/test/
* Update ScalaTest deprecations.
* Update scalatest from 3.0.8 to 3.1.0; apply auto fix for deprecations
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Corrects behavior under write collisions
* Avoids heavily refactoring pass
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* Change VerilogMemDelays to put new Statements at end of Module
Fixes #547
This is instead of putting them right after the modified DefMemory which could
result in use before declaration errors for things that feed into the new
logic.
* Adds tests that show VerilogMemDelays crashing. (#792)
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