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path: root/src/test/scala/firrtlTests/UnitTests.scala
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2021-03-29Fix RemoveAccesses, delete CSESubAccesses (#2157)Jack Koenig
CSESubAccesses was intended to be a simple workaround for a quadratic performance bug in RemoveAccesses but ended up having tricky corner cases and was hard to get right. The solution to the RemoveAccesses bug--quadratic expansion of dynamic indexes of vecs of aggreate type--turned out to be quite simple and makes CSESubAccesses much less useful and not worth fixing. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-08-25Inline Boolean Expressions (#1817)Albert Chen
The following conditions must be satisfied to inline: 1. has type Utils.BoolType 2. is bound to a DefNode with name starting with '_' 3. is bound to a DefNode with a source locator that points at the same file and line number. If it is a MultiInfo source locator, the set of file and line number pairs must be the same. Source locators may point to different column numbers. 4. InlineBooleanExpressionsMax has not been exceeded 5. is not a Mux Also updates the Verilog emitter to break up lines greater than 120 characters
2020-08-14All of src/ formatted with scalafmtchick
2020-03-17[RFC] Factor out common test classes; package them (#1412)David Biancolin
* Pull out common test utilities into a separate package * Project a fat jar for test utilities Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-02-12Removed unused imports in src/test/ (#1381)Jim Lawson
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-01-15improve the tail ir usability. (#1241)Sequencer
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2019-09-16Rename gender to flowSchuyler Eldridge
The following names are changed: - gender -> flow - Gender -> Flow - MALE -> SourceFlow - FEMALE -> SinkFlow - BIGENDER -> DuplexFlow - UNKNOWNGENDER -> UnknownFlow Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-22Add Width Constraints with Annotations (#956)Albert Chen
* refactor InferWidths to allow for extra contraints, add InferWidthsWithAnnos * add test cases * add ResolvedAnnotationPaths trait to InferWidthsWithAnnos * remove println * cleanup tests * remove extraneous constraints * use foreachStmt instead of mapStmt * remove support for aggregates * fold InferWidthsWithAnnos into InferWidths * throw exception if ref not found, check for annos before AST walk
2019-01-23Improve Shl codegen; eliminate Shlw WIR node (#994)Andrew Waterman
* Improve Shl codegen; eliminate Shlw WIR node If we emit shl(x, k) as {x, k'h0} instead of (x << k), then there's no need for Verilog-specific padding in the PadWidths pass. Avoiding the redundant padding improves compiler/simulator performance and renders Shlw unnecessary. * [skip formal checks] Add test
2018-10-31Remove all uses of get_flip and deprecateJack Koenig
It is O(n) and every use is in an O(n) iteration resulting in O(n^2). Same information can be extracted from create_exps which happens to also be called at every use of get_flip.
2018-06-11Add utilities for UInt and SInt literals (#815)Jack Koenig
Also minor cleanup to literal construction in Visitor
2018-02-27Refactor Annotations (#721)Jack Koenig
- Old Annotation renamed to deprecated LegacyAnnotation - Annotation is now a trait that can be extended - New JsonProtocol for Annotation [de]serialization - Replace AnnotationMap with AnnotationSeq - Deprecate Transform.getMyAnnotations - Update Transforms - Turn on deprecation warnings - Remove deprecated Driver.compile - Make AnnotationTests abstract with Legacy and Json subclasses - Add functionality to convert LegacyAnnotations of built-in annos This will give a noisy warning and is more of a best effort than a robust solution. Fixes #475 Closes #609
2018-02-22Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, ↵Adam Izraelevitz
but not Emitter. (#717)
2017-12-22API change: out-of-bounds vec accesses now invalid, not first element (#685)Adam Izraelevitz
[skip formal checks] Generate nicer name for remove accesses
2017-08-23Reorder port and wire assignments in Verilog (#641)Adam Izraelevitz
* Reorder port and wire assignments in Verilog * Fixed up syntax
2017-06-28Promote ConstProp to a transformJack Koenig
2017-03-09Sint tests and change in serialization (#456)Adam Izraelevitz
SInt representation is no longer 2's complement, but instead a positive number (hex or base 10) that is optionally preceded by a sign (-+).
2017-03-06Add ability to emit 1 file per module (#443)Jack Koenig
Changes Emitters to also be Transforms and use Annotations for both telling an emitter to do emission as well as getting the emitted result. Helper functions ease the use of the new interface. Also adds a FirrtlExecutionOptions field as well as a command-line option. Use of Writers in Compilers and Emitters is now deprecated.
2016-12-08Clk2clock - rename the implicit "clk" module input "clock" (#387)Jim Lawson
* Rename implict module "clk" input to "clock". This doesn't rename all the "self-contained" test instances. nor the memory "clk" enables, nor the implict module "clk"s in the regress .fir files. * Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances. This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.
2016-12-05Add check for muxing between clocks (#360)Jack Koenig
Also run CheckTypes after ExpandWhens Fixes #330
2016-11-21Bugfix: exponential runtime of pull muxes (#379)Adam Izraelevitz
2016-11-07Added underscore to GEN, now its _GEN (#362)Adam Izraelevitz
Prefix temporary names with underscores so Verilator won't trace them Use verilator argument "--trace-underscore" if you want to trace these signals
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-11-04Refactor Compilers and Transformsjackkoenig
* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers * Transforms define inputForm and outputForm * Custom transforms can be inserted at runtime into compiler or the Driver * Current "built-in" custom transforms handled via above mechanism * Verilog-specific passes moved to the Verilog emitter
2016-11-01Fix Match Error in Check Types on Partial Connect (#359)Jack Koenig
Fixes #329
2016-09-08remove Utils.{AND, OR, NOT, EQV}Donggyu Kim
hidden const props not desirable
2016-08-04Addd check: bits, tail, head arg widthazidar
2016-08-01Refactor RemoveAccesses and fix bug #210.azidar
Added corresponding unit test.
2016-06-10API Cleanup - ASTJack
trait AST -> abstract class FirrtlNode Move all IR to new package ir Add import of firrtl.ir._
2016-05-24Added Errors class and fixed tests.azidar
Canonicalizes catching/throwing PassExceptions.
2016-05-24add better type mismatch error messageColin Schmidt
also check for it int unittest
2016-05-12Implement File Infojackkoenig
2016-05-10Add test suite for Constant PropagationAdam Izraelevitz
Add unit tests for splitting expressions and padding widths
2016-04-26Test that nested expressions don't make it to the EmitterAndrew Waterman
2016-04-26Fixed the check for bundle equality to allow relative flips to be wrong, but ↵Adam Izraelevitz
the leaf directions are the same
2016-04-16Add license to testsjackkoenig
2016-04-09Adds check for type of DefRegister initializationjackkoenig
Fixes #89
2016-04-09Fix bundle type equalityAdam Izraelevitz
Was not checking for length of bundles, so if the bundles matched but one had more fields, it was not caught.
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