sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2020-09-16	Change to Apache 2.0 License (#1901)	Chick Markley

2020-08-14	All of src/ formatted with scalafmt	chick

2020-05-13	consolidated wire+assign to just wire, with expression inlined (#1600)	Murali Vijayaraghavan
	* consolidated wire <type> x; assign x = y; to wire <type> x = y; * Remove dead code from Emitter.scala Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-03-17	[RFC] Factor out common test classes; package them (#1412)	David Biancolin
	* Pull out common test utilities into a separate package * Project a fat jar for test utilities Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-02-12	Removed unused imports in src/test/ (#1381)	Jim Lawson
	Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2018-05-15	Replace truncating add and sub with addw/subw (#800)	Jack Koenig
	Replaces old VerilogWrap which didn't work with split expressions and was actually buggy anyway. This functionality reduces unnecessary intermediates in emitted Verilog.