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Problem: MemConf serialization of MemPorts was not deterministic
and the ordering seems to have changed as we move projects to 2.13
Downstream project can be adversely affected by changes in ordering
This changes specifies as specific ordering that should be compatible with
the historical one.
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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BlackBoxSourceHelper should only run late in compilation to allow
transforms to tweak its behavior (eg. changing BlackBoxTargetDirAnno).
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* ReplaceMemMacros: add target rename test case
* ReplaceMemMacros: rename references to instances
* fix renaming for deduped mems
* use grouped DummyAnnos to preserve order
* Apply suggestions from code review
Co-authored-by: Jack Koenig <koenig@sifive.com>
* run scalafmt
* flatten targets
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add GenVerilogMemBehaviorModelAnno & vlsiMemGen
* Add CLI support for GenVerilogMemBehaviorModelAnno
* Add simple test for GenVerilogMemBehaviorModelAnno
* Fix for review
1. rename case class Port(prefix, `type`) to Port(prefix, portType)
2. fix AnnotatedMemoriesAnnotation collect function.
3. fix bug that ModuleName is not correct.
* Format DumpMemoryAnnotations & ReplSeqMemTests
* Fix for review
1. Inline genDecl, genPortSpec, genSequential, genCombinational
2. Add DefAnnotatedMemory informations in header
3. Change helpText
4. Check output Verilog by Verilator, the code is from FirrtlRunners#lintVerilog
* Fix ReadWritePort mask name
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* remove all deprecations, switch to new API.
* Add MemLibOutConfigFileAnnotation to replace ConfWriter.
* Inline CreateMemoryAnnotations in ReplSeqMem.
* Dont use ConfWriter anymore.
* Fix ReplSeqMemTests, rewrite checkMemConf to directly read from annoation.
* Fix for review.
0. Since DependencyAPI only initiate transform only once, ListBuffer is
dangerous to use, remove defAnnotatedMemories from Transform.
1. Add trait HasAnnotatedMemories to store ListBuffer,
MemLibOutConfigFileAnnotation also extends from which now.
* Use two annotations converting and storing DefMemory.
0. rewrite CreateMemoryAnnotations to match ReplSeqMemAnnotation
creating PinAnnotation.
1. add DumpMemoryAnnotations to convert from
AnnotatedMemoriesCollectorAnnotation to MemLibOutConfigFileAnnotation
2. refactor MemLibOutConfigFileAnnotation and remove
HasAnnotatedMemories
3. add private AnnotatedMemoriesCollectorAnnotation to store mutable
DefAnnotatedMemory
4. change ReplSeqMem to SeqTransform
* Fix for review.
0. replace AnnotatedMemoriesCollectorAnnotation with immutable
AnnotatedMemoriesAnnotation.
1. add ListBuffer[DefAnnotatedMemory] in ReplaceMemMacros.execute.
* private functions in ReplaceMemMacros transform.
* scalafmt
* remove ConfWriter API.
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* Fix bug in Uniquify clobbering DefInstance types
* Change ReplaceMemTransform to not run Uniquify nor fixups
Use invalidation as mechanism for rerunning resolution passes
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* Pull out common test utilities into a separate package
* Project a fat jar for test utilities
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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This reverts commit eabc38559b7634ff7147aa0ab3d71e78558d5162.
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* Consume NoDedupMemAnnotations in ResolveMemoryReference
The ComponentName being pointed to by the annotation no longer exists
after ReplaceSeqMems so we should consume the annotations
* Support renaming in ReplaceMemMacros
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Types containing bundles can't generally be converted to a single mask granularity
* Update ReplSeqMemTests to check for illegal masks
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Fixes a threading bug in where lazy reading of file
caused a problem for multithreaded access to the that was read.
Changes all uses of io.Source to use new API
getText
getLines
getTextResource
getLinesResouce
Make style to only import FileUtils and not its methods
So code is more explicit as e.g. FileUtils.getText()
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should be parsable without excepting (#1060)
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* Copy MemConf.scala from ucb-bar/barstools#35 into memlib.
This provides a data structure wrapper around the existing memory conf format
which contains both reading and writing methods, making it easier to write code
that needs to read the format.
* Add MemConf tests and use a Map[MemPort, Int] for port lists instead of a Seq[MemPort] which is a bit less fragile.
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Previously, mems marked no dedup would prevent mems with the same
instance name in other modules from deduping
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[skip formal checks] LEC passes with Formality
* Improve code generation for smem RW-port wmode port
A common case for these port-enables is
wen = valid & write
ren = valid & !write
which the RW-port transform currently turns into
en = (valid & write) | (valid & !write)
wmode = valid & write
because it proved `wen` and `ren` are mutually exclusive via `write`.
Synthesis tools can trivially optimize `en` to `valid`, so that's not a
problem, but the wmode field can't be optimized if going into a black box.
This PR instead sets `wmode` to whatever node was used to prove
mutual exclusion, which is always a simpler expression. In this case:
en = (valid & write) | (valid & !write)
wmode = write
* In RemoveCHIRRTL, infer mask relative to port definition
Previously, it was inferred relative to the memory definition causing
the mask condition to be redundantly conjoined with the enable signal.
Also enable ReplSeqMems to ignore all ValidIfs (not just on Clocks) to
improve QoR.
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- Old Annotation renamed to deprecated LegacyAnnotation
- Annotation is now a trait that can be extended
- New JsonProtocol for Annotation [de]serialization
- Replace AnnotationMap with AnnotationSeq
- Deprecate Transform.getMyAnnotations
- Update Transforms
- Turn on deprecation warnings
- Remove deprecated Driver.compile
- Make AnnotationTests abstract with Legacy and Json subclasses
- Add functionality to convert LegacyAnnotations of built-in annos
This will give a noisy warning and is more of a best effort than a
robust solution.
Fixes #475 Closes #609
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Performs DCE by constructing a global dependency graph starting with top-level
outputs, external module ports, and simulation constructs as circuit sinks.
External modules can optionally be eligible for DCE via the
OptimizableExtModuleAnnotation.
Dead code is eliminated across module boundaries. Wires, ports, registers, and
memories are all eligible for removal. Components marked with a
DontTouchAnnotation will be treated as a circuit sink and thus anything that
drives such a marked component will NOT be removed.
This transform preserves deduplication. All instances of a given DefModule are
treated as the same individual module. Thus, while certain instances may have
dead code due to the circumstances of their instantiation in their parent
module, they will still not be removed. To remove such modules, use the
NoDedupAnnotation to prevent deduplication.
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* Added pass name to debug logger
* Addresses #459. Rewords transform annotations API.
Now, any annotation not propagated by a transform is considered deleted.
A new DeletedAnnotation is added in place of it.
* Added more stylized debugging style
* WIP: make pass transform
* WIP: All tests pass, need to pull master
* Cleaned up PR
* Added rename updates to all core transforms
* Added more rename tests, and bugfixes
* Renaming tracks non-leaf subfields
E.g. given:
wire x: {a: UInt<1>, b: UInt<1>[2]}
Annotating x.b will eventually annotate x_b_0 and x_b_1
* Bugfix instance rename lowering broken
* Address review comments
* Remove check for seqTransform, UnknownForm too restrictive check
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Now, any annotation not propagated by a transform is considered deleted.
A new DeletedAnnotation is added in place of it.
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Changes Emitters to also be Transforms and use Annotations for both
telling an emitter to do emission as well as getting the emitted result.
Helper functions ease the use of the new interface. Also adds a
FirrtlExecutionOptions field as well as a command-line option. Use of
Writers in Compilers and Emitters is now deprecated.
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This allows the replseqmem transform to not deduplicate
some memories, based on their name.
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* type conversions between sint/fixed and uint added at memory interfaces for replseqmem
* turns out asFixed requires bp as constant in PrimOps (really should be documented)
* fixed legalizeconnects to handle FixedPt
* added tests for replseqmem failure with signed types
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* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.
* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.
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Restricts annotations to be string-based (and thus less typesafe)
Makes annotations more easily serializable and interact with Chisel
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Replace with more sensible comment to see LICENSE rather than including the
whole license in every file
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* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers
* Transforms define inputForm and outputForm
* Custom transforms can be inserted at runtime into compiler or the Driver
* Current "built-in" custom transforms handled via above mechanism
* Verilog-specific passes moved to the Verilog emitter
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* Keep package name + directory structure consistent
This annoyed me so heres a PR
* fix InferReadWrite references
* delete .ConvertFixedToSInt.scala.swo
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* Reorganized memory blackboxing
Moved to new package memlib
Added comments
Moved utility functions around
Removed unused AnnotateValidMemConfigs.scala
* Fixed tests to pass
* Use DefAnnotatedMemory instead of AppendableInfo
* Broke passes up into simpler passes
AnnotateMemMacros ->
(ToMemIR, ResolveMaskGranularity)
UpdateDuplicateMemMacros ->
(RenameAnnotatedMemoryPorts, ResolveMemoryReference)
* Fixed to make tests run
* Minor changes from code review
* Removed vim comments and renamed ReplSeqMem
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* Addressed the fact that a node can be connected to itself (updating reg)
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* Bug fix -- remove all empty expressions after ReplSeqMem passes
* Added test to make sure ReplSeqMem can handle BundleType SMem (EmptyExpression leakage)
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This test is breaks with any minor change to code generation.
It should be replaced with a more robust test.
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