sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2021-08-02	add emitter for optimized low firrtl (#2304)	Kevin Laeufer
	* rearrange passes to enable optimized firrtl emission * Support ConstProp on padded arguments to comparisons with literals * Move shr legalization logic into ConstProp Continue calling ConstProp of shr in Legalize. Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-11-12	Fix RemoveWires handling of invalidated non-UInt wires (#1949)	Jack Koenig
	It would replace them with a validif node with a UIntLiteral which can lead to type errors.
2020-09-16	Change to Apache 2.0 License (#1901)	Chick Markley

2020-08-14	All of src/ formatted with scalafmt	chick

2020-07-29	[2.13] toSeq, Unit -> (), and postfix fixes	Kevin Laeufer

2020-07-29	InferTypes: fix bugs with unknown widths on ports and memories (#1769)	Kevin Laeufer
	* InferTypesFlowsAndKindsSpec: test the results of InferTypes, ResolveKinds and ResolveFlows * Don't use passes sub-package in tests This changes two test files using the "passes" sub-package to "firrtl.passes". This allows a new "firrtlTests.passes" package to be freely created and used without a name collision. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * ResolveFlows: only depends on types and working ir The types are needed to know the orientation of a bundle field of a SubField node. * InferTypes: fix bugs with unknown widths on ports and memories * LoweringCompileSpec: Uniquify pass moved Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-03-17	[RFC] Factor out common test classes; package them (#1412)	David Biancolin
	* Pull out common test utilities into a separate package * Project a fat jar for test utilities Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-02-12	Removed unused imports in src/test/ (#1381)	Jim Lawson
	Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2019-05-04	Add register init to RemoveWires dependencies (#1078)	Schuyler Eldridge
	Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-14	Asynchronous Reset (#1011)	Jack Koenig
	Fixes #219 * Adds AsyncResetType (similar to ClockType) * Registers with reset signal of type AsyncResetType are async reset registers * Registers with async reset can only be reset to literal values * Add initialization logic for async reset registers
2018-08-07	Make RemoveWires properly include registers in dependency graph	Jack Koenig
	Fixes a bug where registers could be instantiated after nodes that referred to them Also add WRef.apply utility for nodes
2018-06-13	Resolve register clock dependencies in RemoveWires (#823)	Schuyler Eldridge
	Candidate fix for #749 This adds DefRegister netlist ordering to RemoveWires Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2017-12-12	Add RemoveWires transform	Jack Koenig
	This transform replaces all wires with nodes in a legal, flow-forward order