| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-05-04 | Add LegalizeAndReductionsTransform | Jack Koenig |
| 2020-05-01 | Add missing invalidations to some transforms (#1541) | Schuyler Eldridge |
| 2020-04-13 | Ensure PadWidths is run in mverilog compiler | Albert Magyar |
| 2020-04-07 | Fix dynamic SubAccess of zero-length vectors (#1450) | Albert Magyar |
| 2020-03-12 | Add Support for FPGA Bitstream Preset-registers (#1050) | John's Brew |
| 2020-03-11 | Migrate to DependencyAPI | Schuyler Eldridge |
 |
index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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