sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2021-08-02	remove LoweringCompilersSpec (#2310)	Kevin Laeufer
2021-08-02	add emitter for optimized low firrtl (#2304)	Kevin Laeufer
2021-04-06	Deprecate InlineCasts, add InlineAcrossCasts (#2146)	Jack Koenig
2021-03-29	Fix RemoveAccesses, delete CSESubAccesses (#2157)	Jack Koenig
2021-03-04	CSE SubAccesses (#2099)	Jack Koenig
2021-02-01	Deprecate ToWorkingIR (#2028)	Schuyler Eldridge
2020-10-26	fix for LoweringCompilersSpec.	Jiuyang liu
2020-09-16	Change to Apache 2.0 License (#1901)	Chick Markley
2020-08-25	Inline Boolean Expressions (#1817)	Albert Chen
2020-08-14	All of src/ formatted with scalafmt	chick
2020-08-13	Deprecate support for Scala 2.11 (#1842)	Jack Koenig
2020-08-13	Cleanup Named Targets (#1311)	Schuyler Eldridge
2020-08-12	Combined Uniquify and LowerTypes pass (#1784)	Kevin Laeufer
2020-08-10	scalatest: upgrade to 3.2.1 (#1831)	Kevin Laeufer
2020-07-29	RemoveWires: improve dependencies and declare ResolveKinds as an invalidation...	Kevin Laeufer
2020-07-29	InferTypes: fix bugs with unknown widths on ports and memories (#1769)	Kevin Laeufer
2020-07-25	Integrate new transforms with firrtl.stage.Forms (#1754)	Schuyler Eldridge
2020-07-16	Remove overlapping inputForm=LowForm tests	Schuyler Eldridge
2020-06-26	Enable ConvertAsserts in default Verilog compiler	Albert Magyar
2020-06-23	Basic model checking API (#1653)	Tom Alcorn
2020-06-19	RemoveIntervals: invalidate InferTypes and ResolveKinds (#1689)	Albert Chen
2020-05-04	Add LegalizeAndReductionsTransform	Jack Koenig
2020-05-01	Add missing invalidations to some transforms (#1541)	Schuyler Eldridge
2020-04-13	Ensure PadWidths is run in mverilog compiler	Albert Magyar
2020-04-07	Fix dynamic SubAccess of zero-length vectors (#1450)	Albert Magyar
2020-03-12	Add Support for FPGA Bitstream Preset-registers (#1050)	John's Brew
2020-03-11	Migrate to DependencyAPI	Schuyler Eldridge