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| author | Albert Magyar | 2020-06-25 15:13:07 -0700 |
|---|---|---|
| committer | Albert Magyar | 2020-06-26 11:08:42 -0700 |
| commit | cbfb32dc90f25c814898add3eff9b332b6021e5b (patch) | |
| tree | db21fe781e9d6bf04ccc3bed963c4fd97bf5ff6f /src/test/scala/firrtlTests/LoweringCompilersSpec.scala | |
| parent | 425354a493126fe365237491d29dd73d1209a44e (diff) | |
Enable ConvertAsserts in default Verilog compiler
Diffstat (limited to 'src/test/scala/firrtlTests/LoweringCompilersSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/LoweringCompilersSpec.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala index 75f2ea02..82750fdf 100644 --- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala +++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala @@ -354,6 +354,7 @@ class LoweringCompilersSpec extends FlatSpec with Matchers { val tm = (new TransformManager(Seq(Dependency[firrtl.MinimumVerilogEmitter], Dependency[Transforms.LowToLow]))) val patches = Seq( Add(63, Seq( + Dependency(firrtl.transforms.formal.ConvertAsserts), Dependency[firrtl.transforms.formal.RemoveVerificationStatements], Dependency[firrtl.transforms.LegalizeAndReductionsTransform])) ) @@ -367,6 +368,7 @@ class LoweringCompilersSpec extends FlatSpec with Matchers { val tm = (new TransformManager(Seq(Dependency[firrtl.VerilogEmitter], Dependency[Transforms.LowToLow]))) val patches = Seq( Add(70, Seq( + Dependency(firrtl.transforms.formal.ConvertAsserts), Dependency[firrtl.transforms.formal.RemoveVerificationStatements], Dependency[firrtl.transforms.LegalizeAndReductionsTransform])) ) |