sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2021-11-30	[deprecation clean up] remove trait firrtl.util.BackendCompilationUtilities ↵	Jiuyang Liu
	(#2423) Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-11-23	fix tests that depend on Driver (#2429)	Jiuyang Liu
	Co-authored-by: sinofp <sinofp@tuta.io>
2020-09-16	Change to Apache 2.0 License (#1901)	Chick Markley

2020-08-14	All of src/ formatted with scalafmt	chick

2020-05-18	Fix equivalence tests (#853)	Albert Chen
	* - modify firrtlEquivalenceTest to use yosys equiv_simple/equiv_induct instead of miter - add RemoveValidIf pass to MinimumLowFirrtlOptimization * add EquivalenceTest to FirrtlSpec.scala, make classes in IntegrationSpec.scala abstract * change types of inputForm/outputForm to CircuitForm * change EquivalenceTest message * remove ICache equivalence tests * fix rebase errors * Add Ops scalatests to LEC suite * Only run compiler-path-comparison LEC tests on Ops design * Fixup issues with merge Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-03-17	[RFC] Factor out common test classes; package them (#1412)	David Biancolin
	* Pull out common test utilities into a separate package * Project a fat jar for test utilities Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-02-12	Removed unused imports in src/test/ (#1381)	Jim Lawson
	Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-01-07	Redirect testing shell commands to logger	Jack Koenig
	This includes the built-in functions in BackendCompilationUtilities which are a public API
2019-03-29	Faster reg constprop (#1067)	Albert Magyar
	* Improve memoization for register const prop
2018-02-21	Change primop arg type (#587)	Adam Izraelevitz
	* Changed primops to not accept mixed-type args * Changed return type of sub of two uints to uint * Added negative tests * Removed rocket.fir. Manually changed RocketCore to not mix mul arg types. Added integration tests * Clarified test description and remove println * Fixed use of throwInternalError
2017-06-27	Emitting reg update mux tree, only walk netlist for wires and nodes	Jack Koenig
	Fixes bug where the Verilog emitter could pull the next value for a register that feeds a second register, removing the first register from the second register's update.
2017-04-18	"Scope" test resource (top.cpp). (#398)	Jim Lawson
	Jar resources (unlike classes) are typically not scoped. This can create collisions if we have similarly named resources in multiple jars, especially when merging multiple projects in an IDE. Give this resource a distinct name to avoid colliding with chisel3 top.cpp.
2017-03-15	Use newer rocket regression spec without comb loop	Albert Magyar

2017-03-06	Add ability to emit 1 file per module (#443)	Jack Koenig
	Changes Emitters to also be Transforms and use Annotations for both telling an emitter to do emission as well as getting the emitted result. Helper functions ease the use of the new interface. Also adds a FirrtlExecutionOptions field as well as a command-line option. Use of Writers in Compilers and Emitters is now deprecated.
2016-11-04	Cleanup license at top of every file (#364)	Jack Koenig
	Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-10-26	Improve integration test API and add support for Verilog resources	jackkoenig
	Change integration tests to be classes that extend abstract classes. This allows them to be run in parallel. Also expand API to support Verilog resources in integration tests.
2016-09-14	Added Rob.fir for regression testing (#258)	Donggyu

2016-05-24	Add integration test for single-ported memory	jackkoenig

2016-04-16	Add license to tests	jackkoenig

2016-03-10	Add support for right shift by amount larger than argument width	jackkoenig

2016-03-03	Add some integration tests: successful compilation and execution	jackkoenig