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* test: add LeanTransformSpec to replace the old SimpleTransformSpec
SimpleTransformSpec isn't simple anymore!
* AnnotationTests: remove deprecated Compiler code
* LeanTransformSpec: implicitly add right EmitCircuitAnnotation
* AsyncResetSpec: move to new lean spec
* CheckCombLoopsSpec: remove deprecated Compiler code
* ChirrtlMemSpec: remove deprecated compiler code
* CompilerTest: remove use of deprecated Compiler API
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* Absorb WRef into Reference
* Absorb WSubField into SubField
* Absorb WSubIndex into SubIndex
* Absorb WSubAccess into SubAccess
* Absorb WDefInstance into DefInstance
------------------------- API CHANGE SEVERITY --------------------------
This is projected to not break source-level compatibility with any known
user code. However, it will break *binary* compatibility with all
existing user FIRRTL passes, as is generally allowed with major
releases of FIRRTL.
--------------------------- DESCRIPTION --------------------------------
Previously, there were several nodes in WIR.scala that had a one-to-one
correspondance with existing nodes in the standard firrtl.ir hierarchy.
These nodes would have a case class resembling the corresponding
standard IR node, but with the addition of one or more "analysis"
fields.
Since these fields (such as kind) represent helpful info that can be
invalidated or set to Unknown (e.g. UnknownKind for Kind), it does not
cause any issues to simply include these fields on any in-memory
representation of FIRRTL IR. Although other systems for tracking FIRRTL
analyses have evolved over time, the ubiquity of pattern-matching on
these fields has lead most core and custom transforms to be written
against WIR, rather than IR.
This PR unifies the IRs by adding the fields that would be in an
"augmented" WIR node directly into the corresponding IR node; i.e., the
"type" and "kind" fields from WRef are added directly to the definition
of the Reference case class, while these "repetitive" WIR case classes
are removed entirely.
-------------------- SOURCE-COMPATIBILITY ADAPTERS ---------------------
Several object methods are added to WIR.scala to maintain
source-compatiblity for passes that used WIR. These objects define
factory methods and unapply methods, so passes that relied on implicit
case class factories or pattern matching for the removed WIR types will
remain perfectly source-compatible. However, these do not guarantee
compatibility at the binary level.
The types of the removed WIR case classes are also added as type aliases
to the top-level firrtl package, which allows code that relies on
explicit constructor calls or reflection to retain source-compatibility.
Finally, additional explicit factory methods are added to the companion
objects of the newly-augmented IR case classes, which allows user code
to avoid having to specify any of the new analysis fields. Existing code
that created non-WIR IR nodes will be able to continue using the
previous factory signatures, which will cause all omitted analysis
fields to be set to Unknown.
---------------------- UNMITIGATED API CHANGES -------------------------
While passes that used WIR will be source-compatible with this change,
there is one significant change that affects any pass currently using
non-WIR IR: the signatures of pattern-matching cases for Reference,
SubField, SubIndex, SubAccess, and DefInstance must change to
accommodate the extra fields.
This cannot be worked at the API level due to restrictions on unapply
overloading, but it could theoretically be solved with macros or other
static rewriting. However, only four core transforms (RemoveProto,
ToWorkingIR, Dedup, and RemoveChirrtl) use non-WIR IR, and it is
expected that no user code currently relies on it, so the expected
migration strategy is simply to change the small fraction of code
relying on these nodes.
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* Pull out common test utilities into a separate package
* Project a fat jar for test utilities
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Give better error when mport references non-existent memory
* Closes #796
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- Old Annotation renamed to deprecated LegacyAnnotation
- Annotation is now a trait that can be extended
- New JsonProtocol for Annotation [de]serialization
- Replace AnnotationMap with AnnotationSeq
- Deprecate Transform.getMyAnnotations
- Update Transforms
- Turn on deprecation warnings
- Remove deprecated Driver.compile
- Make AnnotationTests abstract with Legacy and Json subclasses
- Add functionality to convert LegacyAnnotations of built-in annos
This will give a noisy warning and is more of a best effort than a
robust solution.
Fixes #475 Closes #609
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but not Emitter. (#717)
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Changes Emitters to also be Transforms and use Annotations for both
telling an emitter to do emission as well as getting the emitted result.
Helper functions ease the use of the new interface. Also adds a
FirrtlExecutionOptions field as well as a command-line option. Use of
Writers in Compilers and Emitters is now deprecated.
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* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.
* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.
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Restricts annotations to be string-based (and thus less typesafe)
Makes annotations more easily serializable and interact with Chisel
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Replace with more sensible comment to see LICENSE rather than including the
whole license in every file
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* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers
* Transforms define inputForm and outputForm
* Custom transforms can be inserted at runtime into compiler or the Driver
* Current "built-in" custom transforms handled via above mechanism
* Verilog-specific passes moved to the Verilog emitter
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