aboutsummaryrefslogtreecommitdiff
path: root/src/test/scala/firrtlTests/CheckSpec.scala
AgeCommit message (Collapse)Author
2021-04-16Make InferTypes error on enable conditions > 1-bit wide (#2182)Jack Koenig
2021-02-17Allow Side Effecting Statement to have Names (#2057)Kevin Laeufer
* firrtl: add optional statement labels for stop, printf, assert, assume and cover * test: parsing of statement labels * ir: ensure that name is properly retained * SymbolTable: add support for labled statements * test: parsing statement labels * test: lower types name collisions with named statements * ignore empty names * Inline: deal with named and unnamed statements * RemoveWires: treat stop, printf and verification statements as "others" * test: fix InlineInstance tests * DeadCodeEliminations: statements are now als declarations * CheckHighForm: ensure that statement names are not used as references * CheckSpec: throw error if statement name collides * add pass to automatically add missing statement names * check: make sure that two statements cannot have the same name * stmtLabel -> stmtName * scalafmt * add statement names to spec * spec: meta data -> metadata * EnsureStatementNames: explain naming algorithm * remove returns * better namespace use * ir: add CanBeReferenced trait * ir: add newline as jack requested
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-08-14All of src/ formatted with scalafmtchick
2020-08-01Error on ExtModules w/ same defname, diff. ports (#1734)Schuyler Eldridge
* Use signed output in LargeParamExecutionTest Change the Verilog used in LargeParamExecutionTest to match its ExtModule specification. An ExtModule with an SInt port should map to a separate Verilog module with a signed port and this is disjoint from an ExtModule with a UInt port. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Error on ExtModules w/ same defname, diff. ports Adds a high form check to ensure that external modules that have the same defname also have exactly the same ports. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-27Add Conditionally scoping tests to CheckSpecAlbert Magyar
* Add specific test for shadowing
2020-03-25Update scalatest 3.1.0 (#1383)Jim Lawson
* Removed unused imports in src/test/ * Update ScalaTest deprecations. * Update scalatest from 3.0.8 to 3.1.0; apply auto fix for deprecations Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-03-16Check for collision of defnames with Module namesAlbert Magyar
* Fixes #1096
2020-03-16Check for module name conflictsAlbert Magyar
* Fixes #1436
2020-03-06Check sign of primop constants where appropriate (#1421)Albert Magyar
* Avoid IndexOutOfBoundsException when Bits has too few consts * Check for negative consts in all relevant primops * Use BigInt for all checks on primop constants
2019-09-16Rename gender to flowSchuyler Eldridge
The following names are changed: - gender -> flow - Gender -> Flow - MALE -> SourceFlow - FEMALE -> SinkFlow - BIGENDER -> DuplexFlow - UNKNOWNGENDER -> UnknownFlow Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-07Check mems for legal latencies; ban zero write latency. (#1147)Albert Magyar
* Check mems for legal latencies; ban zero write latency. * Trigger
2019-08-07DRY check chirrtl (#1148)Albert Magyar
* Avoid redundancy between CheckChirrtl and CheckHighForm, add more checks * Add test case for illegal Chirrtl memory in HighForm
2019-02-25Detect and error on registers with flip in type (#1031)Albert Magyar
2019-02-22Add Width Constraints with Annotations (#956)Albert Chen
* refactor InferWidths to allow for extra contraints, add InferWidthsWithAnnos * add test cases * add ResolvedAnnotationPaths trait to InferWidthsWithAnnos * remove println * cleanup tests * remove extraneous constraints * use foreachStmt instead of mapStmt * remove support for aggregates * fold InferWidthsWithAnnos into InferWidths * throw exception if ref not found, check for annos before AST walk
2018-09-26Enforce port uniqueness in Chirrtl/High ChecksSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-02-08CheckHighForm should check that Bits MSB >= LSB (#738)Schuyler Eldridge
Fixes #700 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2017-12-20Verify shl/shr amount is > 0 (#710)Jim Lawson
Fixes #527
2017-05-03Add checks on register clock and reset types (#33) (#553)Albert Magyar
Remove infix notation on calls with side effects.
2016-12-08Clk2clock - rename the implicit "clk" module input "clock" (#387)Jim Lawson
* Rename implict module "clk" input to "clock". This doesn't rename all the "self-contained" test instances. nor the memory "clk" enables, nor the implict module "clk"s in the regress .fir files. * Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances. This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-08-16add test case for clock type connection (#239)mwachs5
2016-07-25Detects and flags cyclic module loopschick
2016-06-10API Cleanup - ASTJack
trait AST -> abstract class FirrtlNode Move all IR to new package ir Add import of firrtl.ir._
2016-05-24Added Errors class and fixed tests.azidar
Canonicalizes catching/throwing PassExceptions.
2016-05-12Implement File Infojackkoenig
2016-04-26Add test for recursive check for whether BundleType contains flipsAdam Izraelevitz
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 20:23:52 +0000