index
:
sfcX
1.6.x
master
sfc-scala3
Scala FIRRTL Compiler for chiselX
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
test
/
scala
/
firrtlTests
/
AttachSpec.scala
Age
Commit message (
Expand
)
Author
2020-09-16
Change to Apache 2.0 License (#1901)
Chick Markley
2020-08-14
All of src/ formatted with scalafmt
chick
2020-03-17
[RFC] Factor out common test classes; package them (#1412)
David Biancolin
2020-02-12
Removed unused imports in src/test/ (#1381)
Jim Lawson
2019-02-22
Add Width Constraints with Annotations (#956)
Albert Chen
2018-06-06
ConstProp attached wires if there is also a port (#818)
Jack Koenig
2018-03-21
GroupModule Transform (#766)
Adam Izraelevitz
2017-12-27
Removed top preamble (#640)
Adam Izraelevitz
2017-06-12
Fixes a typo in the verilog `elsif code generation (#603)
Shreesha Srinath
2017-05-11
Improved Global Dead Code Elimination (#549)
Jack Koenig
2017-03-06
Add ability to emit 1 file per module (#443)
Jack Koenig
2017-02-14
Add support for Analog types in partial connect (#435)
Jack Koenig
2017-02-07
Rework Attach to work on arbitrary Analog hierarchies (#415)
Jack Koenig
2016-12-08
Clk2clock - rename the implicit "clk" module input "clock" (#387)
Jim Lawson
2016-11-23
Stringified annotations (#367)
Adam Izraelevitz
2016-11-04
Cleanup license at top of every file (#364)
Jack Koenig
2016-11-04
Add a pass to deduplicate modules
azidar
2016-11-04
Refactor Compilers and Transforms
jackkoenig
2016-09-25
Spec features added: AnalogType and Attach (#295)
Adam Izraelevitz