All of src/ formatted with scalafmt

1 files changed, 129 insertions, 162 deletions

diff --git a/src/test/scala/firrtlTests/AttachSpec.scala b/src/test/scala/firrtlTests/AttachSpec.scala
index e4acc735..709e3692 100644
--- a/src/test/scala/firrtlTests/AttachSpec.scala
+++ b/src/test/scala/firrtlTests/AttachSpec.scala
@@ -9,12 +9,12 @@ import firrtl.testutils._
 
 class InoutVerilogSpec extends FirrtlFlatSpec {
 
-  behavior of "Analog"
+  behavior.of("Analog")
 
   it should "attach a module input source directly" in {
     val compiler = new VerilogCompiler
     val input =
-     """circuit Attaching :
+      """circuit Attaching :
         |  module Attaching :
         |    input an: Analog<3>
         |    inst a of A
@@ -25,32 +25,32 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
         |  module B:
         |    input an2: Analog<3> """.stripMargin
     val check =
-     """module Attaching(
-       |  inout  [2:0] an
-       |);
-       |  A a (
-       |    .an1(an)
-       |  );
-       |  B b (
-       |    .an2(an)
-       |  );
-       |endmodule
-       |module A(
-       |  inout  [2:0] an1
-       |);
-       |endmodule
-       |module B(
-       |  inout  [2:0] an2
-       |);
-       |endmodule
-       |""".stripMargin.split("\n") map normalized
+      """module Attaching(
+        |  inout  [2:0] an
+        |);
+        |  A a (
+        |    .an1(an)
+        |  );
+        |  B b (
+        |    .an2(an)
+        |  );
+        |endmodule
+        |module A(
+        |  inout  [2:0] an1
+        |);
+        |endmodule
+        |module B(
+        |  inout  [2:0] an2
+        |);
+        |endmodule
+        |""".stripMargin.split("\n").map(normalized)
     executeTest(input, check, compiler, Seq(dontDedup("A"), dontDedup("B")))
   }
 
   it should "attach two instances" in {
     val compiler = new VerilogCompiler
     val input =
-     """circuit Attaching :
+      """circuit Attaching :
         |  module Attaching :
         |    inst a of A
         |    inst b of B
@@ -60,24 +60,24 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
         |  module B:
         |    input an: Analog<3>""".stripMargin
     val check =
-     """module Attaching(
-       |);
-       |  wire [2:0] _GEN_0;
-       |  A a (
-       |    .an(_GEN_0)
-       |  );
-       |  B b (
-       |    .an(_GEN_0)
-       |  );
-       |endmodule
-       |module A(
-       |  inout  [2:0] an
-       |);
-       |module B(
-       |  inout  [2:0] an
-       |);
-       |endmodule
-       |""".stripMargin.split("\n") map normalized
+      """module Attaching(
+        |);
+        |  wire [2:0] _GEN_0;
+        |  A a (
+        |    .an(_GEN_0)
+        |  );
+        |  B b (
+        |    .an(_GEN_0)
+        |  );
+        |endmodule
+        |module A(
+        |  inout  [2:0] an
+        |);
+        |module B(
+        |  inout  [2:0] an
+        |);
+        |endmodule
+        |""".stripMargin.split("\n").map(normalized)
     executeTest(input, check, compiler, Seq(dontTouch("A.an"), dontDedup("A")))
   }
 
@@ -85,12 +85,12 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
     val compiler = new VerilogCompiler
     val input =
       """circuit Attaching :
-         |  module Attaching :
-         |    wire x: Analog
-         |    inst a of A
-         |    attach (x, a.an)
-         |  module A:
-         |    input an: Analog<3> """.stripMargin
+        |  module Attaching :
+        |    wire x: Analog
+        |    inst a of A
+        |    attach (x, a.an)
+        |  module A:
+        |    input an: Analog<3> """.stripMargin
     val check =
       """module Attaching(
         |);
@@ -99,7 +99,7 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
         |    .an(x)
         |  );
         |endmodule
-        |""".stripMargin.split("\n") map normalized
+        |""".stripMargin.split("\n").map(normalized)
     executeTest(input, check, compiler, Seq(dontTouch("Attaching.x")))
   }
 
@@ -107,14 +107,14 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
     val compiler = new VerilogCompiler
     val input =
       """circuit Attaching :
-         |  module Attaching :
-         |    input an: Analog<3>
-         |    wire x: Analog
-         |    inst a of A
-         |    attach (x, a.an)
-         |    attach (x, an)
-         |  module A:
-         |    input an: Analog<3> """.stripMargin
+        |  module Attaching :
+        |    input an: Analog<3>
+        |    wire x: Analog
+        |    inst a of A
+        |    attach (x, a.an)
+        |    attach (x, an)
+        |  module A:
+        |    input an: Analog<3> """.stripMargin
     val check =
       """module Attaching(
         |  inout [2:0] an
@@ -123,20 +123,19 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
         |    .an(an)
         |  );
         |endmodule
-        |""".stripMargin.split("\n") map normalized
+        |""".stripMargin.split("\n").map(normalized)
     executeTest(input, check, compiler, Seq(dontTouch("Attaching.x")))
   }
 
-
   it should "attach multiple sources" in {
     val compiler = new VerilogCompiler
     val input =
       """circuit Attaching :
-         |  module Attaching :
-         |    input a1 : Analog<3>
-         |    input a2 : Analog<3>
-         |    wire x: Analog<3>
-         |    attach (x, a1, a2)""".stripMargin
+        |  module Attaching :
+        |    input a1 : Analog<3>
+        |    input a2 : Analog<3>
+        |    wire x: Analog<3>
+        |    attach (x, a1, a2)""".stripMargin
     val check =
       """module Attaching(
         |  inout  [2:0] a1,
@@ -151,7 +150,7 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
         |    alias a1 = a2;
         |  `endif
         |endmodule
-        |""".stripMargin.split("\n") map normalized
+        |""".stripMargin.split("\n").map(normalized)
     executeTest(input, check, compiler)
   }
 
@@ -159,10 +158,10 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
     val compiler = new VerilogCompiler
     val input =
       """circuit Attaching :
-         |  module Attaching :
-         |    input foo : { b : UInt<3>, a : Analog<3> }
-         |    output bar : { b : UInt<3>, a : Analog<3> }
-         |    bar <- foo""".stripMargin
+        |  module Attaching :
+        |    input foo : { b : UInt<3>, a : Analog<3> }
+        |    output bar : { b : UInt<3>, a : Analog<3> }
+        |    bar <- foo""".stripMargin
     // Omitting `ifdef SYNTHESIS and `elsif verilator since it's tested above
     val check =
       """module Attaching(
@@ -174,7 +173,7 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
         |  assign bar_b = foo_b;
         |  alias bar_a = foo_a;
         |endmodule
-        |""".stripMargin.split("\n") map normalized
+        |""".stripMargin.split("\n").map(normalized)
     executeTest(input, check, compiler)
   }
 
@@ -182,14 +181,14 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
     val compiler = new VerilogCompiler
     val input =
       """circuit Attaching :
-         |  module Attaching :
-         |    input a : Analog<32>
-         |    input b : Analog<32>
-         |    input c : Analog<32>
-         |    input d : Analog<32>
-         |    attach (a, b)
-         |    attach (c, b)
-         |    attach (a, d)""".stripMargin
+        |  module Attaching :
+        |    input a : Analog<32>
+        |    input b : Analog<32>
+        |    input c : Analog<32>
+        |    input d : Analog<32>
+        |    attach (a, b)
+        |    attach (c, b)
+        |    attach (a, d)""".stripMargin
     val check =
       """module Attaching(
         |  inout  [31:0] a,
@@ -199,19 +198,19 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
         |);
         |    alias a = b = c = d;
         |endmodule
-        |""".stripMargin.split("\n") map normalized
+        |""".stripMargin.split("\n").map(normalized)
     executeTest(input, check, compiler)
 
     val input2 =
       """circuit Attaching :
-         |  module Attaching :
-         |    input a : Analog<32>
-         |    input b : Analog<32>
-         |    input c : Analog<32>
-         |    input d : Analog<32>
-         |    attach (a, b)
-         |    attach (c, d)
-         |    attach (d, a)""".stripMargin
+        |  module Attaching :
+        |    input a : Analog<32>
+        |    input b : Analog<32>
+        |    input c : Analog<32>
+        |    input d : Analog<32>
+        |    attach (a, b)
+        |    attach (c, d)
+        |    attach (d, a)""".stripMargin
     val check2 =
       """module Attaching(
         |  inout  [31:0] a,
@@ -221,14 +220,14 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
         |);
         |    alias a = b = c = d;
         |endmodule
-        |""".stripMargin.split("\n") map normalized
+        |""".stripMargin.split("\n").map(normalized)
     executeTest(input2, check2, compiler)
   }
 
   it should "infer widths" in {
     val compiler = new VerilogCompiler
     val input =
-     """circuit Attaching :
+      """circuit Attaching :
         |  module Attaching :
         |    input an: Analog
         |    inst a of A
@@ -236,70 +235,65 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
         |  module A:
         |    input an1: Analog<3>""".stripMargin
     val check =
-     """module Attaching(
-       |  inout  [2:0] an
-       |);
-       |  A a (
-       |    .an1(an)
-       |  );
-       |endmodule
-       |module A(
-       |  inout  [2:0] an1
-       |);
-       |endmodule""".stripMargin.split("\n") map normalized
+      """module Attaching(
+        |  inout  [2:0] an
+        |);
+        |  A a (
+        |    .an1(an)
+        |  );
+        |endmodule
+        |module A(
+        |  inout  [2:0] an1
+        |);
+        |endmodule""".stripMargin.split("\n").map(normalized)
     executeTest(input, check, compiler)
   }
 
   it should "not error if not isinvalid" in {
     val compiler = new VerilogCompiler
     val input =
-     """circuit Attaching :
+      """circuit Attaching :
         |  module Attaching :
         |    output an: Analog<3>
         |""".stripMargin
     val check =
-     """module Attaching(
-       |  inout  [2:0] an
-       |);
-       |endmodule""".stripMargin.split("\n") map normalized
+      """module Attaching(
+        |  inout  [2:0] an
+        |);
+        |endmodule""".stripMargin.split("\n").map(normalized)
     executeTest(input, check, compiler)
   }
   it should "not error if isinvalid" in {
     val compiler = new VerilogCompiler
     val input =
-     """circuit Attaching :
+      """circuit Attaching :
         |  module Attaching :
         |    output an: Analog<3>
         |    an is invalid
         |""".stripMargin
     val check =
-     """module Attaching(
-       |  inout  [2:0] an
-       |);
-       |endmodule""".stripMargin.split("\n") map normalized
+      """module Attaching(
+        |  inout  [2:0] an
+        |);
+        |endmodule""".stripMargin.split("\n").map(normalized)
     executeTest(input, check, compiler)
   }
 }
 
 class AttachAnalogSpec extends FirrtlFlatSpec {
   private def executeTest(input: String, expected: Seq[String], passes: Seq[Pass]) = {
-    val c = passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
-      (c: Circuit, p: Pass) => p.run(c)
+    val c = passes.foldLeft(Parser.parse(input.split("\n").toIterator)) { (c: Circuit, p: Pass) =>
+      p.run(c)
     }
-    val lines = c.serialize.split("\n") map normalized
+    val lines = c.serialize.split("\n").map(normalized)
 
-    expected foreach { e =>
+    expected.foreach { e =>
       lines should contain(e)
     }
   }
 
   "Connecting analog types" should "throw an exception" in {
-    val passes = Seq(
-      ToWorkingIR,
-      CheckHighForm,
-      ResolveKinds,
-      InferTypes,
-      CheckTypes)
+    val passes = Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes)
     val input =
       """circuit Unit :
         |  module Unit :
@@ -307,38 +301,28 @@ class AttachAnalogSpec extends FirrtlFlatSpec {
         |    output x: Analog<1>
         |    x <= y""".stripMargin
     intercept[CheckTypes.InvalidConnect] {
-      passes.foldLeft(parse(input)) {
-        (c: Circuit, p: Pass) => p.run(c)
+      passes.foldLeft(parse(input)) { (c: Circuit, p: Pass) =>
+        p.run(c)
       }
     }
   }
 
   "Declaring register with analog types" should "throw an exception" in {
-    val passes = Seq(
-      ToWorkingIR,
-      CheckHighForm,
-      ResolveKinds,
-      InferTypes,
-      CheckTypes)
+    val passes = Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes)
     val input =
       """circuit Unit :
         |  module Unit :
         |    input clk: Clock
         |    reg r: Analog<2>, clk""".stripMargin
     intercept[CheckTypes.IllegalAnalogDeclaration] {
-      passes.foldLeft(parse(input)) {
-        (c: Circuit, p: Pass) => p.run(c)
+      passes.foldLeft(parse(input)) { (c: Circuit, p: Pass) =>
+        p.run(c)
       }
     }
   }
 
   "Declaring memory with analog types" should "throw an exception" in {
-    val passes = Seq(
-      ToWorkingIR,
-      CheckHighForm,
-      ResolveKinds,
-      InferTypes,
-      CheckTypes)
+    val passes = Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes)
     val input =
       """circuit Unit :
         |  module Unit :
@@ -350,38 +334,28 @@ class AttachAnalogSpec extends FirrtlFlatSpec {
         |      write-latency => 1
         |      read-under-write => undefined""".stripMargin
     intercept[CheckTypes.IllegalAnalogDeclaration] {
-      passes.foldLeft(parse(input)) {
-        (c: Circuit, p: Pass) => p.run(c)
+      passes.foldLeft(parse(input)) { (c: Circuit, p: Pass) =>
+        p.run(c)
       }
     }
   }
 
   "Declaring node with analog types" should "throw an exception" in {
-    val passes = Seq(
-      ToWorkingIR,
-      CheckHighForm,
-      ResolveKinds,
-      InferTypes,
-      CheckTypes)
+    val passes = Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes)
     val input =
       """circuit Unit :
         |  module Unit :
         |    input in: Analog<2>
         |    node n = in """.stripMargin
     intercept[CheckTypes.IllegalAnalogDeclaration] {
-      passes.foldLeft(parse(input)) {
-        (c: Circuit, p: Pass) => p.run(c)
+      passes.foldLeft(parse(input)) { (c: Circuit, p: Pass) =>
+        p.run(c)
       }
     }
   }
 
   "Attaching a non-analog expression" should "not be ok" in {
-    val passes = Seq(
-      ToWorkingIR,
-      CheckHighForm,
-      ResolveKinds,
-      InferTypes,
-      CheckTypes)
+    val passes = Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes)
     val input =
       """circuit Unit :
         |  module Unit :
@@ -394,21 +368,14 @@ class AttachAnalogSpec extends FirrtlFlatSpec {
         |  extmodule B:
         |    input o: Analog<2>""".stripMargin
     intercept[CheckTypes.OpNotAnalog] {
-      passes.foldLeft(parse(input)) {
-        (c: Circuit, p: Pass) => p.run(c)
+      passes.foldLeft(parse(input)) { (c: Circuit, p: Pass) =>
+        p.run(c)
       }
     }
   }
 
   "Inequal attach widths" should "throw an exception" in {
-    val passes = Seq(
-      ToWorkingIR,
-      CheckHighForm,
-      ResolveKinds,
-      InferTypes,
-      CheckTypes,
-      new InferWidths,
-      CheckWidths)
+    val passes = Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes, new InferWidths, CheckWidths)
     val input =
       """circuit Unit :
         |  module Unit :
@@ -418,8 +385,8 @@ class AttachAnalogSpec extends FirrtlFlatSpec {
         |  extmodule A :
         |    output o: Analog<2> """.stripMargin
     intercept[CheckWidths.AttachWidthsNotEqual] {
-      passes.foldLeft(CircuitState(parse(input), UnknownForm)) {
-        (c: CircuitState, p: Transform) => p.runTransform(c)
+      passes.foldLeft(CircuitState(parse(input), UnknownForm)) { (c: CircuitState, p: Transform) =>
+        p.runTransform(c)
       }
     }
   }