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path: root/src/test/scala/firrtlTests/AsyncResetSpec.scala
AgeCommit message (Collapse)Author
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-08-22Async reset tieoff bug (#1854)David Biancolin
* Elide emission of literals for async reset in sensitivity lists * Deprecate LegalizeClocksTransform Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-08-14All of src/ formatted with scalafmtchick
2020-08-14tests: Decrease Dependency on Deprecated APIs (#1839)Kevin Laeufer
* test: add LeanTransformSpec to replace the old SimpleTransformSpec SimpleTransformSpec isn't simple anymore! * AnnotationTests: remove deprecated Compiler code * LeanTransformSpec: implicitly add right EmitCircuitAnnotation * AsyncResetSpec: move to new lean spec * CheckCombLoopsSpec: remove deprecated Compiler code * ChirrtlMemSpec: remove deprecated compiler code * CompilerTest: remove use of deprecated Compiler API
2020-07-23Update negative literal emission (#1782)Albert Chen
* test const prop of addition of negative literals * Emitter: handle minimum negative values correctly * update expected verilog in AsyncResetSpec
2020-04-20Avoid casting 2-bit interval to AsyncReset in testAlbert Magyar
2020-04-14Add Paul's async-reset self-init case as a testAlbert Magyar
2020-04-14Allow casts in AsyncReset literal value check (#1523)Jack Koenig
Chisel emits all literals as UInts cast to the correct type, make CheckResets support casts when checking that async reset registers are reset to literal values. Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-17[RFC] Factor out common test classes; package them (#1412)David Biancolin
* Pull out common test utilities into a separate package * Project a fat jar for test utilities Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-02-06Add constant prop to async regs (#1355)Adam Izraelevitz
* Add constant prop to async regs * Added another test of no reset value but constant assignment * Clarify name of updateNodeMap * Update constant assignment of async reset to not be inferred as a latch, works with donttouch * Revert "Update constant assignment of async reset to not be inferred as a latch, works with donttouch" This reverts commit 952bf38127cb32f814496a2b4b3bfb173d532728.
2020-02-06Emit 'else' case for trivial-valued async reset regs to avoid latches (#1359)Albert Magyar
2020-01-07Remove unnecessary $signed casts for PrimOps in Verilog EmitterJack Koenig
[skip formal checks] Adds new InlineCastsTransform to the VerilogEmitter which removes Statements that do nothing but cast by inlining the cast Expression
2019-11-05Move CheckResets after CheckCombLoops (#1224)Jack Koenig
Recursive literal lookup needs to be guarded against combinational loops Added a test-case to illustrate the issue when CheckResets is run before CheckCombLoops
2019-10-18Upstream intervals (#870)Adam Izraelevitz
Major features: - Added Interval type, as well as PrimOps asInterval, clip, wrap, and sqz. - Changed PrimOp names: bpset -> setp, bpshl -> incp, bpshr -> decp - Refactored width/bound inferencer into a separate constraint solver - Added transforms to infer, trim, and remove interval bounds - Tests for said features Plan to be released with 1.3
2019-08-13Infer reset (#1068)Jack Koenig
* Add abstract "Reset" which can be inferred to AsyncReset or UInt<1> * Enhance async reset initial value literal check to support aggregates
2019-02-14Asynchronous Reset (#1011)Jack Koenig
Fixes #219 * Adds AsyncResetType (similar to ClockType) * Registers with reset signal of type AsyncResetType are async reset registers * Registers with async reset can only be reset to literal values * Add initialization logic for async reset registers
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